[SI-LIST] Signal Integrity Jobs at Cisco

We are looking a senior level signal integrity engineer in Enterprise
Switching Technology Group (ESTG), Cisco, San Jose. The description is
given below. If you are interested, please send your resume or contact
me directly.
 
Best Regards,
 
Amit P. Agrawal, Ph.D.
Senior Manager, Hardware Engineering
Enterprise Switching Technology Group
Cisco, San Jose, CA
amiagra2@xxxxxxxxx
(408) 424-2732 (Office)
(408) 666-8452 (Cell) 
__________________________________________________________
 
JOB DESCRIPTION FOR SIGNAL INTEGRITY ENGINEER
 
An experienced signal integrity engineer is being sought for design and
analysis of high speed interfaces and power distribution network. The
successful candidate will be part of signal integrity technology team
and participate in the definition of chip, package, printed circuit
board (PCB), and system interconnects.  Within a concurrent engineering
environment, the individual will be part of a larger team with system
architects, logic designers, ASIC engineers, and SI engineers in
creation of next generation networking products.
 
 This group works on present and next-generation cost-sensitive yet high
performance and high volume products.
 
 Your responsibilities will include but not limited to: 
 

- Working experience in high speed serial I/O applications, PLLs, CDR,
transceiver/SERDES operations
- Definition of signaling and package technology for high performance
ASICs
- Simulating and/or analyzing and/or generating power delivery network
requirements 
- Understanding signal integrity and timing in order to budget and
evaluate trade-offs between design parameters to determine a solution

  space that is high volume manufacturability 
- Generating the routing requirements and electrical margins for
specific interfaces and verifying their correctness 
- Designing and conducting detailed testing and measurements to collect
data for validation and correlation of design analysis
- Making recommendations to modify lab equipment and/or processes to
establish or improve process feasibility and/or capability and 

  increase efficiency

 

 

Typically requires MSEE/CS combined with 5-7 years of related
experience, or BSEE/CS combined with 7-10+ yrs related experience.
Proficiency with spice (or equivalent) circuit simulation, field-solver
and time/frequency domain analysis, familiarity with high speed serdes
design, PLL design and LVDS, SST, CML and other high-performance I/O
technologies, ASIC design experience with I/O selection and
simulation/validation, solid background on transmission line theory are
necessary. In depth understanding of electromagnetics is plus.
Experience with available CAD/CAE tools such as HSPICE, SiSoft, HFSS,
CST, Sigrity Speed 2000, PowerSI,  Si-Wave, Paksi-E, Power-grid,
Spicelink, TDA, Apache Redhawk/CPM, Agilent ADS, and Cadence SI tools or
related tools.  Experience in correlating simulation results with lab
measurements using oscilloscopes, TDRs, VNAs, and spectrum analyzers is
a plus. Self motivation, teamwork and strong communication skills are
essential.


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