[SI-LIST] Re: Scaling effects on on-chip power grids

  • From: Christopher Jakubiec <Christopher.Jakubiec@xxxxxxx>
  • To: cyr_1976@xxxxxxxxx
  • Date: Fri, 19 Mar 2004 08:49:24 -0800

Yiran,

I'm not sure that there is a hard fast (normal) rule for a scaling ratio from
0.18um to 0.13um.  Is the metal changing from aluminum to copper?  How has the
dielectric between metal layers changed?  What are the thickness and pitch 
limits?
These are the types of issues that can significantly vary your results based on 
the 
specific technology you are using for your design.  Hopefully your Fab has 
already 
characterized the metal layers and can provide you results that you can use for 
your 
design rules.  TSMC does this as a matter of practice.  The last technology 
shift that
I worked on was 0.25um to 0.13um, we both modeled and created a test chip 
(measured)
to characterize the 8 layers of metal.  We then modified our original wire 
models based
on the measured results.

Regards,

Chris Jakubiec
Sun Microsystems



Yiran Chen wrote:
> 
> Hi, guys
> 
> Now I am studying the on-chip power grids scaling issue. It is claimed that 
> the on-chip power grids is hard to scaled. Could someone give me a example to 
> show what is the normal rule to caculate the scaling ratio of powr supply 
> grid.
> 
> For example, when we scale our technolgoy from .18um to .13 um, for the metal 
> 6 which is used to implement power supply mesh, do we need to shrink the 
> width, thickness and pitch of our power supply mesh?
> 
> If so ( I believe so), what is the normal ratio? How does this ratio affect 
> the RLC of power supply mesh?
> 
> Thanks.
> 
> Yiran
> 
> 
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