Darn, sorry guys, but I lost over half of my comments to John on the last E-mail. I didn't save it, so here's a brief summary of what "disappeared." The result is minimal disturbance (under the circumstances) because of the use of the low inductance current path and the lowest current density entry point to the internal circuits of the PCB. RE: Capacitors around the periphery I recommended PROVISIONS for "spoiler" capacitors be spaced around the ring at varying intervals. Because the ring forms a loop antenna that is resonant at a low to intermediate frequency, a susceptibility coul be encountered, depending on the using environment. If so, addition of either capacitors or low value damping resistors could be used to "spoil" or significantly reduce the susceptibility. These mounting provisions are not recommended to be populated unless a problem is encountered. The guard ring approach solved many ESD problems, particularly on portable designs. I presented the concept in lectures across the US and Europe, as well as incorporating custom variations in many designs over the years. Perhaps many designers now use the concept without understanding whether they have need for it in their particular design. I had considerably more to comment, but don't have any more time now. Have fun, Mike Michael L. Conn Owner/Principal Consultant Mikon Consulting Cell: 408-821-9843 *** Serving Your Needs with Technical Excellence *** ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List archives are viewable at: //www.freelists.org/archives/si-list or at our remote archives: http://groups.yahoo.com/group/si-list/messages Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu