[SI-LIST] Re: SSTL termination resistor power

George:
 
One interesting question is that how chip pass spec testing when shipped to 
customer? I guess customer will do the ODT calibration which will cover all 
frequency range.
 
One possibilty of the issue is that we have a long run "1", ODT will show very 
high impedance and voltage will pile up to "vdd", when there is a quick "0" 
toggle, assume sin wave form, the AC voltage change will be "vdd/2" ideally. 
What receiver side see for this "0" is "vdd-vdd/2=vdd/2", which is the common 
mode voltage of SSTL. It is hard for receiver to recognize it.
 
I am not sure that whether I missed anything in above analysis. Maybe the 
circuit speed is very fast and still cross vdd/2 in 1 UI. However, this will 
eat your voltage swing margin anyway, since a lot of swing is wasted along the 
"long frequency component".
 
If the whole industry does it, there might be some reason. I might want to do 
some real home work on it to get 1st hand sense. But I can not persuade myself 
out of above conclusion. 
 
thanks,
Han

George Tang <gtang@xxxxxxxx> wrote:
Han,

That (DC balance) is not a problem if you design it correctly. We run
Gigabit PRBS data (non-DC-balanced) through AC coupling Caps all weeks long.
Actually, the whole industry does it.

George



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bi Han
Sent: Friday, August 26, 2005 9:05 AM
To: George Tang; List` Si
Subject: [SI-LIST] Re: SSTL termination resistor power


Tang:

Thanks for the information.

One major problem with it, is the different termination impedance for DC-AC
range. If the data is not well coded, like 8B/10B, then could cause problem.

Thanks again for the inputs.
Han
George Tang wrote:
Han,

I have not worked on DDR memory design for over 5 yrs, and I don't remember
what we did before, so don't take my word for it. However, here is
something to think about.
Do an AC 60 ohm termination to gnd with a 1k pullup and 1k pulldown for the
DC voltage bias.
^
|
1K
Driver -->-----------------|
| |
Z |
| 1K
= |
| |
V V


George

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]On Behalf Of Bi Han
Sent: Thursday, August 25, 2005 8:17 AM
To: List` Si
Subject: [SI-LIST] SSTL termination resistor power


SSTL termination might use ODT termination for receiver side.

The implementation is about 120ohm between PAD and VDDQ, another 120ohm
between PAD and VSSQ. Overall AC impedance is about 60ohm.
Since signal is DC coupled, there is DC current burning in terminaion
resistors. If the PCB trace impedance is 60ohm, then the DC current in the
termination resistor is about 20mA. It is so huge that I can not believe
that DDR memory can afford it.

Is there any way to reduce the power?

thanks,
Han

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