[SI-LIST] Re: SSTL_2 doubt

Canes,
Look at the notes 1 and 2 in Table 5a,
and use this
imin=(Vtt-Vout)/(Rt+Rs)

You will see 8.1mA


Cheers,


Kihong



On 6/19/07, Canes Venatici <starsilic@xxxxxxxxx> wrote:
>
> Hi all,
> I thought of finding how 8.1ma (class-I) is arrived.
> Refer to the attachment (taken from JESD8-9B,page6)
>
> if the reciever is to detect a '0', then as per standard,
> ac i/p logic low max = Vref - 0.31 (page 4)
> This tells Vin max = Vref(min) - 0.31
>
> Vref min is 1.13 (table4) and also there is drop of 25mv ac noise on Vref,
> meaning Vref can go to a minimum of 1.13-0.025.
>
> This translates to Vin max= 1.13-0.025-0.31=0.795v
> meaning, for detecting as low by reciever Vin should not exceed 0.795v at
> worst
> conditions.
>
> Now coming to the driver side, Vin is max, if Vtt is maximum.
> So Vin max = Vtt(max) - IRt
> Vttmax=1.42 (table4).
>
> As we know vin should not exceed  0.795,
> 0.795 = 1.42 - IRt
> => I.Rt = 1.42 - 0.795 = 0.625.
>
> This makes 0.625/50 = 12.5mA.
>
> But standard specifies 8.1mA. Where am I wrong...................
>
>
>
>
>
> *Kihong Kim <joshuakh@xxxxxxxxx>* wrote:
>
> Raj,
> I have no idea about how JEDEC arrived that specification but here is how
> I
> understand to give you more...
>
> In digital IC design, what IC designers normally think for their IO buffer
> design is so-called toggling frequency for internal logic building block
> (d-flip/flop etc). If your digital switching frequency is higher than
> that,
> it will treat that as a noise. But if it is within that range, it takes
> the
> switching as a meaningful transition whether or not it is meant to be.
>
> So in order to have IO buffers optimal in terms of SNR(signal in power and
> AC ringing as noise), you want to limit the bandwidth to increase the
> input
> signal sensitivity within a meaningful range.
>
>
> Hope this helps-
>
>
>
>
> Kihong Joshua Kim
>
>
>
>
>
>
>
> SI in Photonics and Electronics
>
>
>
> On 6/18/07, steve weir wrote:
> >
> > raj, the issue is gain bandwidth product.
> >
> > Steve
> > raj singh wrote:
> > > I always get confused with the ac level specs.
> > >
> > > What was JEDEC intent behind including these levels in the spec?
> > >
> > > From the JEDEC Standard documentation I understand that it is to take
> > care of ringing. This means it just to provied extra noise margin over
> dc
> > levels.
> > > Then why mem vendors spec timing with respect to ac levels? I have
> > seen that most of the receivers on these interfaces (HSTL, SSTL*) can
> switch
> > with just Vref +/-20,30mV of input swing. They need very small energy to
> > switch. Much lower than the area under 1V/ns slew and ac-levels.
> > >
> > > Thanks and Regards
> > > Raj
> > >
> > >
> > > Kihong Kim wrote:
> > > I think you need to more specific to get the answer.
> > > But by speculatioin....
> > > If you are comparing DC specificaton to AC specification, you would
> not
> > be
> > > able to derive the numbers by simple math.
> > > It is more like things regarding power applied to logic buffers AND
> > signal
> > > amplitude to logic threshold.
> > >
> > >
> > >
> > > Kihong Joshua Kim
> > >
> > >
> > >
> > >
> > >
> > > SI in Electronics and Photonics
> > >
> > >
> > >
> > > On 6/15/07, Canes Venatici wrote:
> > >
> > >> Hi,
> > >> I'd gone through JEDEC SSTL_2 standard. In that I don't understand
> how
> > >> Vih(ac) min is arrived at Vref+0.31v?
> > >> The delta Vin min is given as 365mV. Then how the difference of
> 0.055vis
> > >> accounted. I tried the noise on Vref may
> > >> be imposed on 365mV, but that is just 25mV.
> > >> Could anyone clarify it?
> > >>
> > >> Thanks
> > >> Canes
> > >>
> > >>
> > >>
> > >>
> > >>
> >
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