[SI-LIST] Re: SPI 4-2 question(s)

The OIF SPI4.2 specification is incomplete in many respects. From our
analysis, it looks like the NPSI (SPI4.2 variant) with the addition of an
accumulated clock jitter specification (jitter components between fD and
fD/1000 of say 0.15UI) at point A, is a less ambiguous TX specification.

Q1: An attempt to add eye mask definitions to the OIF specification was
unsuccessful.

Q2: While it is not clear from the spec., our interpretation is that the
receiver de-skew should track all jitter components below fD/1000.
Commonly used TX structures have little skew making TX DPA unnecessary. I
don't think the spec. allocates the +/- 1UI skew among the RX/TX and
interconnect.

Q3: One could wait until errors are detected to send a training pattern.
Since the specification does not guarantee data bit transitions other than by
using the training pattern, in order for the receiver to track all jitter
below fD/1000, a training pattern is needed every 1000 bit times.

Thanks,
Vinu


Vadim Heyfitch wrote:

>         Hello SI gurus:
>
> It's my understanding that SPI 4-2 has Dynamic Phase Alignment (DPA) =
> that basically centers the RDCLK in the middle of the RDAT eye opening - =
> individually for each of the 16 data bits. Thus, usual =
> source-synchronous timing measurements of Tsu/Thd become irrelevant for =
> SPI4-2. What matters now is the eye opening - both vertical and =
> horizontal.=20
>
> Q1: Is there a eye mask defined for SPI4-2 industry wide? Or does each =
> vendor have its own definition?
>
> With the DPA in play, what is the response time of this de-skewing ckt? =
> Here is why I am asking: the long term jitter, or long term closing of =
> the eye does not matter any more. It's the short term jitter that =
> matters.=20
>
> Q2: What is the response time of the de-skewing mechanism? Is de-skewing =
> done on the receiving end only, or can the launch time at the drives end =
> be DPA'ed?
>
> As I understand it, there is a training sequence sent frequently during =
> initial power up. As the chip warms up and stops drifting, the training =
> is sent less frequently and is controlled by the software. (Correct? Is =
> this standard or vendor specific?) =20
>
> Q3: Does the time interval between consecutive trainings depend on =
> specific application? Does the de-skewing mechanism wait until parity =
> errors are detected before sending the next training pattern. What is =
> the meaningful timing measurement methodology for SPI4-2 simulations?
>
> Q4: The previous level of SPI4, before SPI4-2 (what was its name?): does =
> it exist only as a spec, or has there been silicon sampled? Is SPI4-2 =
> backward compatible
>
> Thanks in advance for offering your insights.
>
> -Vadim Heyfitch
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