[SI-LIST] Re: [!! SPAM] Re: High Speed traces and connectors

Chris
You are thinking even-mode, not common mode.  The differential signal is 
carried on most microstrip traces as 90% even-mode and 10% odd-mode.  
However, it is still a differential excitation, and will "know" to 
become fully odd-mode as it dereferences at a pad with plane relief.  
This can be further tuned and optimized in a 3D full-wave solver.

With common mode excitation, both signal traces carry the same signal 
with the same polarity.  This is propagated as two even-mode waves. When 
the common-mode hits a plane relief on both traces, there can be a huge 
discontinuity, if the return path is not managed well.  This can cause EMI.

Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed® is the registered service mark of
Teraspeed Consulting Group LLC



Cotton, Chris wrote:
>
> Thanks for the clarifications. But as far as the <10% of the energy 
> typically being common mode, wouldn't this depend how tightly or 
> loosely coupled the differential routing is? Although I haven't 
> quantified it for loosely coupled routing I would expect more common 
> mode energy than 10%.
>
>  
>
> ------------------------------------------------------------------------
>
> *From:* Scott McMorrow [mailto:scott@xxxxxxxxxxxxx]
> *Sent:* Wednesday, November 12, 2008 10:35 AM
> *To:* Cotton, Chris
> *Cc:* David Instone; Lakshmi N. Sundararajan - PTU; si-list@xxxxxxxxxxxxx
> *Subject:* Re: [!! SPAM] [SI-LIST] Re: High Speed traces and connectors
>
>  
>
> Chris,
>
> If the plane relief under the pads is done correctly, the differential 
> mode can be tuned to nearly 100 ohms, and the common mode can be 
> well-contained.  In general, we don't much care whether the common 
> mode impedance is well-matched, since it represents <10% of the signal 
> energy typically.  However, it is possible to provide a reasonable 
> impedance match and control of the return path.  These sorts of 
> optimizations are strongly dependent upon the location of the plane 
> underneath the traces and pads.
>
> regards,
>
> Scott
>
>
> Scott McMorrow
> Teraspeed Consulting Group LLC
> 121 North River Drive
> Narragansett, RI 02882
> (401) 284-1827 Business
> (401) 284-1840 Fax
>  
> http://www.teraspeed.com
>  
> Teraspeed® is the registered service mark of
> Teraspeed Consulting Group LLC
>
>
>
> Cotton, Chris wrote:
>
> Thanks David. Yes. I agree. I think we are all directly or indirectly talking 
> about impedance here. My point is that differential signals are not purely 
> differential mode. 
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx> on 
> behalf of David Instone
> Sent: Wed 11/12/2008 5:56 AM
> To: Cotton, Chris
> Cc: Lakshmi N. Sundararajan - PTU; si-list@xxxxxxxxxxxxx 
> <mailto:si-list@xxxxxxxxxxxxx>
> Subject: [SI-LIST] Re: High Speed traces and connectors
>  
> The width of the fingers is set by the requirement to mate with the PCI 
> connector.  The required width is such that if you have any plane 
> anywhere under them their differential impedance will be much lower than 
> the 100 Ohms required, thus in the area of the PCB which is under those 
> fingers there must not be any planes, or traces either.  (That's a plane 
> anywhere in the stackup under those fingers, the board has a thickness 
> defined by the need to mate with that connector.)    You can easily see 
> the effect on a TDR.  Getting the differential impedance right is much 
> more important than any effect on the common mode. 
>  
> Regards
> Dave Instone
> +44 (0)1235 824963
>  
> OXFORD SEMICONDUCTOR LIMITED
> 25 MILTON PARK
> ABINGDON
> OXFORDSHIRE
> OX14 4SH
> Registered in England no 2733820
> Registered Address: As above 
>  
>  
>  
> Cotton, Chris wrote:
>   
>> Correction - The differential mode current should not be
>> affected.
>>  
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx> 
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Cotton, Chris
>> Sent: Tuesday, November 11, 2008 1:31 PM
>> To: Lakshmi N. Sundararajan - PTU; si-list@xxxxxxxxxxxxx 
>> <mailto:si-list@xxxxxxxxxxxxx>
>> Subject: [SI-LIST] Re: High Speed traces and connectors
>>  
>> This is not something that I generally do. That having been said, I
>> assume they are only asking you to remove the immediate or adjacent
>> pwr/gnd plane. If this is the case, the rationale is that the connector
>> pads are much larger than the trace and will look like a capacitive
>> load. Removing the immediate plane will lower the capacitance.
>>  
>> The CM return current has to find a GND pin anyway so I don't think it
>> will be severely impacted. The differential mode current will be
>> affected but difficult to quantify to what degree. I would not make
>> these changes without them providing a technical rationale and
>> assessment of risk.
>>  
>> Chris
>>  
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx <mailto:si-list-bounce@xxxxxxxxxxxxx> 
>> [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Lakshmi N. Sundararajan - PTU
>> Sent: Tuesday, November 11, 2008 12:58 PM
>> To: si-list@xxxxxxxxxxxxx <mailto:si-list@xxxxxxxxxxxxx>
>> Subject: [SI-LIST] High Speed traces and connectors
>>  
>> Hi Team,
>> I had a curious review mentioned on my board for high speed traces
>> for which I could not get a satisfactory explanation.
>>  
>> For all high speed traces from a connector, the review mentioned
>> to remove GND/PWR plane from under the *signal pads* under connector.
>> Even for the PCIE connector, for all the signal pads, the GND/
>> PWR plane was requested to be removed.
>> Now, these are 6Gig and 5Gig high speed signals. If there isnt GND/PWR
>> plane then definetely I would assume there isnt any reference plane for
>> return current.
>>  
>> So, can you experts suggest, whether this is a right thing to do
>> and if so why?
>>  
>> Thanks
>> -LN
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