[SI-LIST] Re: [SPAM] - Re: AC cap placement on Clocks - Email found in subject

Hello Stefan,
please read my posting closely - I did not say placement does not matter. 
I say it does not matter for an "ideal capacitor" (i.e. without any 
mounting or package parasitics, and without any seriel resistance). I also 
give some reasons why some specific placement could be preferable.

Best regards,

Wolfgang






"Stefan Milnor" <stefan.milnor@xxxxxxxxxxxxxx> 
10/22/2009 01:52 PM

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<wolfgang.maichen@xxxxxxxxxxxx>, "Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
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"Sam Pete" <cygnul@xxxxxxxxx>, "icer world" <icermail@xxxxxxxxx>, 
<si-list@xxxxxxxxxxxxx>, <si-list-bounce@xxxxxxxxxxxxx>
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RE: [SPAM] - [SI-LIST] Re: AC cap placement on Clocks - Email found in 
subject






Experts -
 
If the physical placement of the caps does not matter, why do vendors like 
Intel advise us to place them close to the transmitters, for PCIe use?
 
No matter how carefully you place the caps and route the pairs, it seems 
that having them (and the vias and layer changes etc) causes an impedance 
bump of some sort, and for this reason, it would be better to have them 
close to the source package.
 
Just my amateur opinion - Stefan M. @ Kontron 

From: si-list-bounce@xxxxxxxxxxxxx on behalf of 
wolfgang.maichen@xxxxxxxxxxxx
Sent: Thu 10/22/2009 10:15 AM
To: Lee Ritchey
Cc: Sam Pete; icer world; si-list@xxxxxxxxxxxxx; 
si-list-bounce@xxxxxxxxxxxxx
Subject: [SPAM] - [SI-LIST] Re: AC cap placement on Clocks - Email found 
in subject

Hello Sam,
an ideal capacitor will be completely transparent and high-frequency
signal (down to the cutoff frequency - the capacitor C in combination with
the Thevenin-equivalent line impedance of 2*Zo form a high-pass filter
with a time constant of 2*Zo*C). So from that standpoint it does not
matter at all where you place it, as Lee already stated.

Of course a real capacitor always has some parasitic package and mounting
inductance, so if you go to very high frequencies or data rates
(multi-Gbit/sec) you will end up seeing reflections caused by that.
Although at your speeds (below a GHz)  that won't be an issue unless you
reeally mess up the design (e.g. use a through-hole capacitor instead of a
good surface mount ceramic one). In that case it will be better in improve
your design rather than try to find a "sweet spot" for the placement which
will make your design very sensitive against any changes (e.g. line
length, other parasitics). Failing that, the best bet is probably to place
it very close (within ~1/4th of the shortest wavelength of interest, given
by the frequency 0.33/rise_time) to either your driver or your receiver.

The second consideration would be whether you put in the AC coupling
purely for signaling reasons (e.g. to avoid debiasing driver or receiver),
or whether it shall also act as protection. If e.g. it shall protect the
driver against short circuits (e.g. if driver and receiver reside on
different boards that get hot-plugged together), it may be better to place
the cpacitor on the driver side. But that willd depend on the specific
design.

Wolfgang






"Lee Ritchey" <leeritchey@xxxxxxxxxxxxx>
Sent by: si-list-bounce@xxxxxxxxxxxxx
10/22/2009 06:39 AM

To
"icer world" <icermail@xxxxxxxxx>, "Sam Pete" <cygnul@xxxxxxxxx>,
si-list@xxxxxxxxxxxxx
cc

Subject
[SI-LIST] Re: AC cap placement on Clocks






Form  an SI point of view, it does not matter where along the path the
capacitors are placed.


> [Original Message]
> From: icer world <icermail@xxxxxxxxx>
> To: Sam Pete <cygnul@xxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 10/21/2009 8:48:26 PM
> Subject: [SI-LIST] Re: AC cap placement on Clocks
>
> It's hard to say where the AC cap should be placed ,so you'd better do a
simulation if you have device models .
> I'm in doubt that why you use the AC coupling manner since the driver
and
the receiver  are both LVDS level.
>
>
>
> ________________________________
> From: Sam Pete <cygnul@xxxxxxxxx>
> To: si-list@xxxxxxxxxxxxx
> Sent: Thu, October 22, 2009 7:22:17 AM
> Subject: [SI-LIST] AC cap placement on Clocks
>
> Hi All,
> I have a situation like this:
> LVDS Driver, ac cap, LVDS receiver (internal term) 156MHz clock.
> |>-----------------||----------------|>
> |>-----------------||----------------|>
>
>
> What is the optimum place to put coupling cap when the clock is
ac-coupled.
> Should it be close to driver or should it be close to receiver.
>
> From my understanding, the discontinuity should not be visible to the
electrical length of the signal.  Having said that, ac cap should be as
close as possible to Driver.
>
> please share your thoughts.
>
> Thanks
> Sam
>
>
>
> 
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