[SI-LIST] Re: [!! SPAM] Re: 6 layers stackup

Lee, it is important that any test vehicle design is such that it allows 
us to reliably extract a measure of the phenomenon we are interested in 
to the degree of accuracy we seek.  As noted in my previous message, 
John's vehicles used in "RTFT Volume 1", and the subject report both 
suffer badly in this area.  I think part of the problem is that these 
vehicles were intended to do too many things.  A narrower focus might 
well have resulted in much more appropriate designs.

Best Regards,


Steve.

Lee Ritchey wrote:
> What does the test vehicle have to do with it?  Both capacitors are seeing
> the same stackup.  It's apples and apples.   Why 26 layers?  Lots of PCBs
> have 26 layers, pretty much all of them in terabit routers.  This PCB was
> used to test may things besides these two capacitors.
>
> What is being presented is the difference between the two capacitors under
> the same set of test conditions and it is not much.
>
> There are two sets of tests.  One with the capacitors connected to the
> first two planes inside the PCB, which is the lowest added inductance and
> the other is with the capacitors attached to two planes further down in the
> PCB.  
>
>
>   
>> [Original Message]
>> From: Grasso, Charles <Charles.Grasso@xxxxxxxxxxxx>
>> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>; Scott McMorrow
>>     
> <scott@xxxxxxxxxxxxx>
>   
>> Cc: Steve Weir <weirsi@xxxxxxxxxx>; QU Perry
>>     
> <Perry.Qu@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>   
>> Date: 2/26/2008 9:48:30 AM
>> Subject: RE: [SI-LIST] Re: [!! SPAM]  Re: 6 layers stackup
>>
>> Hi Lee,
>>
>> I question the test vehicle. In the paper the test vehicle is 
>> described as:
>>
>> "The PCB has 26 layers of 0.5oz copper planes. The epoxy glass is Isola
>> FR406 with 2-ply 106 glass for all layers.
>> Nominal dielectric thickness of each layer is 3-mils. The total board
>> thickness is 98 mils. The capacitance is 2.6 nF for
>> each voltage plane to ground."
>>
>> My goodness!! 26 layers! I suggest that the sheer number of planes is
>> obfuscating the results and that a better test would be for a board
>> with TWO planes only (suitably positioned to look like a 4 layer
>> stackup).
>>
>> The folks at UMR have shown that when planes are tightly coupled the
>> effect
>> of various positional and attachment parasitics are minimized.
>>
>>
>>
>> Best Regards
>> Charles Grasso
>> Compliance Engineer
>> Echostar Communications Corp.
>> Tel: 303-706-5467
>> Fax: 303-799-6222
>> Cell: 303-204-2974
>> Pager/Short Message: 3032042974@xxxxxxxxx
>> Email: charles.grasso@xxxxxxxxxxxx
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Lee Ritchey
>> Sent: Tuesday, February 26, 2008 9:51 AM
>> To: Scott McMorrow
>> Cc: Steve Weir; QU Perry; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup
>>
>> Guess it's time to cut through the discusson and make some measurements.
>>
>> On my web site, www.speedingedge.com, is a paper titled "Comparison of
>> X2Y
>> vs. 0402 Capacitors for Decoupling" authored by John Zasio.  There is a
>> common test vehicle, the X2Y and the 0402 capacitors being tested are
>> mounted on the same PCB using the manufacturer recommended mounting for
>> the
>> X2Y capacitor and a 4 via mounting for the 0402 capacitor.  The test
>> setup
>> is identical for both capacitors, so the differences in measurements
>> should
>> be only those associated with each capacitor.  The test method is one
>> commonly used in the industry to measure PDS Z vs. F, namely a spectrum
>> analyser with a tracking signal generator.
>>
>> The results speak for themselves.  There is only a slight difference in
>> the
>> performance of the two capacitors suggesting that either the  0402 is a
>> magically very good capacitor- as good as an X2Y or that the X2Y is
>> about
>> the same as an 0402.  The readers can decide for themselves which is the
>> accurate interpretation.
>>
>> My conclusion, along with many others in the industry, is that the X2Y
>> has
>> similar mouning inductance to an 0402 when used on a multilayer PCB.
>> The
>> same can be said for an IDC capacitor.  The IDC measurements are in our
>> book.
>>
>> If those who argue otherwise want to debunk this set of measurements, it
>> is
>> incumbent on them to measure the two styles of capacitors under
>> indentical
>> conditions and post their results.
>>
>> Lee Ritchey
>> Speeding Edge
>>
>>     
>>> [Original Message]
>>> From: Scott McMorrow <scott@xxxxxxxxxxxxx>
>>> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
>>> Cc: Steve Weir <weirsi@xxxxxxxxxx>; QU Perry
>>>       
>> <Perry.Qu@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
>>     
>>> Date: 2/26/2008 7:19:08 AM
>>> Subject: [SI-LIST] Re: [!! SPAM]  Re: 6 layers stackup
>>>
>>> Lee
>>> I apologize for misinterpreting your calculation of capacitor 
>>> inductance.  However, your numbers still do not hold.  Lets take a
>>>       
>> board 
>>     
>>> where the planes are 40 mils down with a via inductance of 17.5 pH/mil
>>>       
>>> per via pair for 0402 capacitors and 5 pH/mil per 6 via mount for X2Y 
>>> capacitor.
>>>
>>> 40 mil case
>>> Via attach inductance = 17.5 pH/mil x 40 = 700 pH
>>> 0402 capacitor inductance = 450 pH
>>> total inductance 0402 capacitor = 1.15 nH
>>>
>>> X2Y capacitor via attach inductance = 5 pH/mil x 40 = 200 pH
>>> X2Y capacitor inductance = 120 pH
>>> total inductance X2Y capacitance = 320 pH
>>>
>>> Inductance ratio  0402 vs. X2Y = 1150/320 = 3.59:1 (planes 40 mils
>>>       
>> down)
>>     
>>> If we perform the same calculations with the planes 20 mils down, we
>>>       
>> get:
>>     
>>> Total inductance 0402 capacitor = 800 pH
>>> Total inductance X2Y capacitor = 220 pH
>>> Inductance ratio 0402 vs. X2Y = 3.64:1
>>>
>>> By virtue of the fact that low inductance capacitors utilize multiple 
>>> vias that take advantage of mutual inductance coupling, there are 
>>> inherent inductance advantages in the body of the capacitor itself and
>>>       
>>> within the coupled via system that penetrates the planes.  For
>>>       
>> example, 
>>     
>>> if you look at an X2Y capacitor via pattern you will see that although
>>>       
>>> there are 6 vias used, there are 4 well-coupled via pairs.  This 
>>> provides lower overall inductance than what would be provided by 3
>>>       
>> sets 
>>     
>>> of spatially isolated via pairs, as is the case with 0402 capacitor 
>>> mounting patterns.
>>>
>>> No matter how we cut it, simulate it, or measure it, a well-mounted
>>>       
>> X2Y 
>>     
>>> capacitor has better than 3:1 performance advantage over an 0402 
>>> capacitor.   It's not magic, it's science.
>>>
>>>
>>> Regards,
>>>
>>> Scott
>>>
>>> Scott McMorrow
>>> Teraspeed Consulting Group LLC
>>> 121 North River Drive
>>> Narragansett, RI 02882
>>> (401) 284-1827 Business
>>> (401) 284-1840 Fax
>>>
>>> http://www.teraspeed.com
>>>
>>> Teraspeed(r) is the registered service mark of
>>> Teraspeed Consulting Group LLC
>>>
>>>
>>>
>>> Lee Ritchey wrote:
>>>       
>>>> I disagree that ultralow inductance capacitors perform significantly
>>>>         
>> better
>>     
>>>> that standard two leaded capacitors such as 0402 and 0603 due to the
>>>>         
>> added
>>     
>>>> inductance associated with the mounting pads and mounting vias.
>>>>         
>> This
>> has
>>     
>>>> been supported many times by physical measurements on real PCBs and
>>>>         
>> is
>>     
>>>> documented in my book, "Right the First Time, A Practical Handbook
>>>>         
>> on
>> High
>>     
>>>> Speed PCB and Systetm Design" as well as in several other sources.
>>>>
>>>> I am mystified at how it can be claimed that this is not so when the
>>>> inductance of the vias connecting capacitors to the associated
>>>>         
>> planes
>>     
>>>> averages something like 35 pH per mil of length- no matter what
>>>>         
>> kind of
>>     
>>>> magical capacitor they are connected to.  It is especially true when
>>>>         
>> one is
>>     
>>>> speaking of a six layer PCB that has planes 20-40 mils below the
>>>>         
>> surface. 
>>     
>>>> That is 0.7 nH to 1.4 nH per lead.  Even if the capacitor has 0.1 nH
>>>> inductance as an IDC capacitor is said to have, the total inductance
>>>>         
>> is
>>     
>>>> driven up near 1 nH.  How can any capacitor make this go away?
>>>>
>>>> It is time to stop pretending that there are magic capacitors out
>>>>         
>> there.
>>     
>>>> Lee Ritchey
>>>> Speeding Edge.
>>>>
>>>>
>>>>   
>>>>         
>>>>> [Original Message]
>>>>> From: steve weir <weirsi@xxxxxxxxxx>
>>>>> To: QU Perry <Perry.Qu@xxxxxxxxxxxxxxxxxx>
>>>>> Cc: <si-list@xxxxxxxxxxxxx>
>>>>> Date: 2/25/2008 11:52:30 AM
>>>>> Subject: [SI-LIST] Re: 6 layers stackup
>>>>>
>>>>> Perry, the discussion has been limited to 4/6 layer boards with a
>>>>>           
>> single 
>>     
>>>>> symmetric power cavity.  The Z axis inductance for an IC or bypass
>>>>>           
>> cap 
>>     
>>>>> to the cavity depends on the distance to the center of the cavity. 
>>>>>           
>> With 
>>     
>>>>> a single, symmetric cavity, that is going to be half the board 
>>>>> thickness.  This is not to be confused with higher layer count
>>>>>           
>> boards 
>>     
>>>>> where we can place at least one modestly thin cavity near the IC / 
>>>>> capacitor mounting surface.  In all cases, the cavity spreading 
>>>>> inductance becomes a limiting factor in PDN impedance.  Cavity
>>>>>           
>> impedance 
>>     
>>>>> varies directly with cavity height.
>>>>>
>>>>> In the case of any almost thickness PCB, the via attachment
>>>>>           
>> structure
>> is 
>>     
>>>>> a significant, if not dominant contributor to the mounted capacitor
>>>>>           
>>>>> inductance, that is the inductance as seen at that attachment point
>>>>>           
>> at 
>>     
>>>>> the planes.  Capacitors like X2Y(r)'s, and IDC(r)'s when properly 
>>>>> attached yield much lower inductance than discrete caps.  This is 
>>>>> readily modeled in any number of tools, and confirmed by properly 
>>>>> constructed experiments.  So low inductance caps still work,
>>>>>           
>> whether
>> or 
>>     
>>>>> not you have a thin cavity, and whether or not the cavity is
>>>>>           
>> adjacent
>> to 
>>     
>>>>> the caps.
>>>>>
>>>>> We are talking about two different resonances.  The resonance that
>>>>>           
>> you 
>>     
>>>>> are referring to are the half-wave modes.  I am talking about the 
>>>>> parallel resonance between the bypass network and the power cavity.
>>>>>           
>>>>> This is the beast that eats most people's lunch.  It is a matter of
>>>>>           
>>>>> capacitance per unit area of the cavity which depends directly on 
>>>>> height, and the area / unit inductance of the bypass network.
>>>>>
>>>>> Best Regards,
>>>>>
>>>>>
>>>>> Steve.
>>>>>
>>>>> QU Perry wrote:
>>>>>     
>>>>>           
>>>>>> Steve:
>>>>>>
>>>>>> My understanding on the impact of thinner power cavity is mainly
>>>>>>             
>> the
>>     
>>>>>> reduction of spread inductance, such that any added benefit of
>>>>>>             
>> IDC/X2Y
>>     
>>>>>> placed at the peripheral of BGA will not be compromised by the
>>>>>>             
>> planes..
>>     
>>>>>> In most applications however, we rely heavily on the decoupling
>>>>>>             
>> caps
>>     
>>>>>> (0402) directly placed underneath BGAs, and in those cases, I
>>>>>>             
>> would
>>     
>>>>>> think thickness of power cavity is not important as the total
>>>>>>             
>> inductance
>>     
>>>>>> looking into PCB from BGA pads to the planes and to the decoupling
>>>>>>             
>> caps
>>     
>>>>>> don't change. Your thoughts ?
>>>>>>
>>>>>> I'm also not clear when you say parallel resonance frequency is
>>>>>>             
>> driven
>>     
>>>>>> by thickness. Comparing Z dimension vs. X/Y for a normal power
>>>>>>             
>> plane/PCB
>>     
>>>>>> thickness, I would say the resonance frequency is mainly
>>>>>>             
>> determined by
>>     
>>>>>> how big the plane is not how thick the cavity ?
>>>>>>
>>>>>> Thanks
>>>>>>
>>>>>> Perry
>>>>>>
>>>>>> ======================================= 
>>>>>>
>>>>>> Perry Qu 
>>>>>>
>>>>>> Design & Qualification, Alcatel-Lucent Canada Inc.
>>>>>>
>>>>>> 600 March Road, Ottawa ON, K2K 2E6, Canada 
>>>>>>
>>>>>> DID: 613-7846720  Fax: 613-5993642 
>>>>>>
>>>>>> Email: perry.qu@xxxxxxxxxxxxxxxxxx 
>>>>>>
>>>>>> ======================================= 
>>>>>>
>>>>>>  
>>>>>>
>>>>>>   
>>>>>>       
>>>>>>             
>>>>>>> -----Original Message-----
>>>>>>> From: si-list-bounce@xxxxxxxxxxxxx 
>>>>>>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
>>>>>>> Sent: Saturday, February 23, 2008 6:44 PM
>>>>>>> To: DAVID CUTHBERT
>>>>>>> Cc: Fernando Yuitiro Mori; si-list@xxxxxxxxxxxxx
>>>>>>> Subject: [SI-LIST] Re: 6 layers stackup
>>>>>>>
>>>>>>> Dave, Fernando my $0.02 on 4/6 layer stack-ups with a single 
>>>>>>> symmetric power cavity:
>>>>>>>
>>>>>>> 1) The Z-axis inductance seen at the IC solder pads to the 
>>>>>>> power cavity is pretty much fixed by:
>>>>>>>
>>>>>>> a. The total thickness of the PCB.
>>>>>>> b. The pin-out of the IC.
>>>>>>> c. The via drill diameter.
>>>>>>>
>>>>>>> 2) Similarly the Z-axis inductance seen between the bypass 
>>>>>>> caps and the power cavity is fixed by:
>>>>>>>
>>>>>>> a. The total thickness of the PCB.
>>>>>>> b. The type of bypass capacitors used.
>>>>>>> c. The via pattern used w/ the bypass caps.
>>>>>>> d. The via drill diameter.
>>>>>>> e. The areal density of the bypass caps used.
>>>>>>>
>>>>>>> b/c/d Determine the mounted inductance of each cap.  X2Y(r)'s 
>>>>>>> and IDC(r)'s yield the best results.  In all cases the via 
>>>>>>> pattern used makes a big difference in the number of caps 
>>>>>>> used and the behavior at parallel resonance.  In my mind it 
>>>>>>> is a lot better to floor plan bypass caps w/ optimal via 
>>>>>>> patterns up front, than to have the PCB designer try to fit 
>>>>>>> them in later.
>>>>>>>
>>>>>>> 3) As the power cavity is made thinner, six notable things
>>>>>>>               
>> happen:
>>     
>>>>>>> a. The horizontal spreading inductance of the planes falls.  
>>>>>>> The extremes for six layer 0.062" stack-ups can be almost 
>>>>>>> 10:1 going from a
>>>>>>> 4 mil to a 38 mil power core.
>>>>>>> b. The high frequency impedance of the power system comes 
>>>>>>> down.  On the bad side one will be in PCB wave effects at 
>>>>>>> lower frequencies.  Detuning w/ discretes takes about the 
>>>>>>> same number of parts independent of the cavity thickness.  
>>>>>>> Tolerances are more forgiving for the thinner cavity.
>>>>>>> c. The parallel resonant frequency of the power system comes 
>>>>>>> down as the square root of the power cavity thickness.  
>>>>>>> Typical resonant frequencies typically vary over a 300MHz to 
>>>>>>> 1.5GHz range depending on bypass scheme over the 4mil to 
>>>>>>> 38mil cavity thicknesses.
>>>>>>> d. The Q of the parallel resonance goes up.  On the good 
>>>>>>> side, higher Qs 
>>>>>>> are generally easier to detune.   The bad side is that the
>>>>>>>               
>> natural 
>>     
>>>>>>> magnitude of Zpeak is fairly independent of the cavity 
>>>>>>> thickness, now it is much more likely to be where there is 
>>>>>>> more signal energy.  The moral here is:  detune the resonance.
>>>>>>> e. Above and below the resonant frequency noise attenuation
>>>>>>>               
>> improves..
>>     
>>>>>>> f. The asymmetry between outer and inner routing layers in a 
>>>>>>> 6 layer stack-up become more pronounced and routing density 
>>>>>>> can suffer severely.  Maintaining 50Ohms and/or acceptable 
>>>>>>> cross talk values on outer layers more than about 10 mils 
>>>>>>> from an image plane demands some rather wide traces and 
>>>>>>> routing pitches.
>>>>>>>
>>>>>>> 4) An S1 G S2 S3 P S4 stack-up works best when the highest 
>>>>>>> speed signals can be broken out and routed completely on S1.  
>>>>>>> Otherwise S1 P S2 S3 G
>>>>>>> S4 is usually better breaking out high speed signals on layer 
>>>>>>> S4 first and layer S3 second, minimizing via stubs.  In 
>>>>>>> either case prioritizing the traces with the most high speed 
>>>>>>> energy to the routing layer(s) adjacent an image plane 
>>>>>>> connected to the dominant coupling rail in the IC will help 
>>>>>>> reduce demands on the PDN.  That rail is usually ground.
>>>>>>>
>>>>>>> Best Regards,
>>>>>>>
>>>>>>> Steve.
>>>>>>>
>>>>>>>
>>>>>>> DAVID CUTHBERT wrote:
>>>>>>>     
>>>>>>>         
>>>>>>>               
>>>>>>>> Fernando,
>>>>>>>> The S1 S2 G P S3 S4 stackup can provide excellent power plane 
>>>>>>>> performance at the expense of S1 and S4. Routing S1 and S4 
>>>>>>>>       
>>>>>>>>           
>>>>>>>>                 
>>>>>>> mostly at 
>>>>>>>     
>>>>>>>         
>>>>>>>               
>>>>>>>> right angles to S2 and
>>>>>>>> S3 can greatly reduce the crosstalk. And using narrow traces to 
>>>>>>>> maintain the Z0 of S1 and S4 will take care of the Z0.
>>>>>>>>
>>>>>>>> I often use S1 G S2 -  S3 P S4 for 6-layer boards. The 
>>>>>>>>       
>>>>>>>>           
>>>>>>>>                 
>>>>>>> signal traces 
>>>>>>>     
>>>>>>>         
>>>>>>>               
>>>>>>>> are nicely isolated with a 62 mil board having spacing like so:
>>>>>>>> 10 mils, 5 mils, 22 mils, 5 mils, 10 mils. The tradeoff is that
>>>>>>>>                 
>> the 
>>     
>>>>>>>> power plane Z0 is about 2X that of a board having 10 mils 
>>>>>>>>       
>>>>>>>>           
>>>>>>>>                 
>>>>>>> between each 
>>>>>>>     
>>>>>>>         
>>>>>>>               
>>>>>>>> layer. The power plane Z0 is still quite low with an inductance
>>>>>>>>                 
>> of 
>>     
>>>>>>>> about 200 pH per square. Contrast this to an S1-G via inductance
>>>>>>>>                 
>> of 
>>     
>>>>>>>> about 300 pH and the plane Z does not dominate things.
>>>>>>>>
>>>>>>>>      Dave Cuthbert
>>>>>>>>      NARTE Certified EMC Engineer
>>>>>>>>      Consulting, SI, EMC, power electronics, analog of all kinds
>>>>>>>>
>>>>>>>>
>>>>>>>> On Wed, Feb 20, 2008 at 2:17 PM, Fernando Yuitiro Mori 
>>>>>>>> <mori@xxxxxxxxxxxxx>
>>>>>>>> wrote:
>>>>>>>>
>>>>>>>>   
>>>>>>>>       
>>>>>>>>           
>>>>>>>>                 
>>>>>>>>> Hi,
>>>>>>>>> I normally use S1 S2 G P S3 S4 for the 6 layers stackup. I 
>>>>>>>>>         
>>>>>>>>>             
>>>>>>>>>                   
>>>>>>> need the 4 
>>>>>>>     
>>>>>>>         
>>>>>>>               
>>>>>>>>> layer with 60 ohms, so there are some problem if I use S1 
>>>>>>>>>         
>>>>>>>>>             
>>>>>>>>>                   
>>>>>>> G S2 S3 P S4?
>>>>>>>     
>>>>>>>         
>>>>>>>               
>>>>>>>>> Regards,
>>>>>>>>>
>>>>>>>>> Fernando Mori
>>>>>>>>>
>>>>>>>>>                   
>> ------------------------------------------------------------------
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>>>>>>>>
>>>>>>>>   
>>>>>>>>       
>>>>>>>>           
>>>>>>>>                 
>>>>>>> --
>>>>>>> Steve Weir
>>>>>>> Teraspeed Consulting Group LLC
>>>>>>> 121 North River Drive
>>>>>>> Narragansett, RI 02882 
>>>>>>>
>>>>>>> California office
>>>>>>> (408) 884-3985 Business
>>>>>>> (707) 780-1951 Fax
>>>>>>>
>>>>>>> Main office
>>>>>>> (401) 284-1827 Business
>>>>>>> (401) 284-1840 Fax 
>>>>>>>
>>>>>>> Oregon office
>>>>>>> (503) 430-1065 Business
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>>>>>>>
>>>>>>> http://www.teraspeed.com
>>>>>>> This e-mail contains proprietary and confidential 
>>>>>>> intellectual property of Teraspeed Consulting Group LLC
>>>>>>> --------------------------------------------------------------
>>>>>>> ----------------------------------------
>>>>>>> Teraspeed(R) is the registered service mark of Teraspeed 
>>>>>>> Consulting Group LLC
>>>>>>>
>>>>>>>
>>>>>>>               
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>>>>> -- 
>>>>> Steve Weir
>>>>> Teraspeed Consulting Group LLC 
>>>>> 121 North River Drive 
>>>>> Narragansett, RI 02882 
>>>>>
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>>>>> (408) 884-3985 Business
>>>>> (707) 780-1951 Fax
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>>>> --------------------------
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>> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>>
>>
>> List technical documents are available at:
>>                 http://www.si-list.net
>>
>> List archives are viewable at:     
>>              http://www.freelists.org/archives/si-list
>> or at our remote archives:
>>              http://groups.yahoo.com/group/si-list/messages
>> Old (prior to June 6, 2001) list archives are viewable at:
>>              http://www.qsl.net/wb6tpu
>>   
>>     
>
>
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>
> or to administer your membership from a web page, go to:
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>
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>
> List technical documents are available at:
>                 http://www.si-list.net
>
> List archives are viewable at:     
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> Old (prior to June 6, 2001) list archives are viewable at:
>               http://www.qsl.net/wb6tpu
>   
>
>
>   


-- 
Steve Weir
Teraspeed Consulting Group LLC 
121 North River Drive 
Narragansett, RI 02882 

California office
(408) 884-3985 Business
(707) 780-1951 Fax

Main office
(401) 284-1827 Business 
(401) 284-1840 Fax 

Oregon office
(503) 430-1065 Business
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http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of 
Teraspeed Consulting Group LLC
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To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

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