[SI-LIST] Re: [!! SPAM] Re: 6 layers stackup

The intent of the test was to compare the two capacitor types to each other
as an IC would see them on a real PCB.  (The test vehicle looks like many
high layer count PCBs that are built every day, so it is a realistic way to
look at these  capacitors.)  After all, that is the end goal, to make
capacitors into good coulomb buckets for the users of charge on a PCB.  To
get wrapped around the axle about the exact inductance of a part is a
sidebar.

Sure, you can argue that the mounting inductance is higher than it needs to
be for the X2Y, but not radically so.  The mounting of the 0402 and its
vias is done this way all the time.  There is no need for a solder dam as
we use solder mask over bare copper and Entec for solder  protection. 
Solder  does not bleed down the holes when boards are built this way.

If you want to debunk this set of tests, build a test PCB with an X2Y and
an 0402 mounted with the recomended mountings and a test vehicle that you
think is appropriate and test the capacitors side by side.  Until that
happens, we have a collosal shouting match going on with insults to good
engineers' professionalism, which is not productive.

Lee Ritchey


> [Original Message]
> From: steve weir <weirsi@xxxxxxxxxx>
> To: <leeritchey@xxxxxxxxxxxxx>
> Cc: Scott McMorrow <scott@xxxxxxxxxxxxx>; QU Perry
<Perry.Qu@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> Date: 2/26/2008 12:21:54 PM
> Subject: [SI-LIST] Re: [!! SPAM]  Re: 6 layers stackup
>
> Lee, it really saddens me to see a person of your stature promoting such 
> bad misinformation in public forums.  While measurements are important, 
> not all measurements are created equal.  Quality measurements are great 
> tools.  Measurements made with faulty rulers are useless junk.
>
> We have conducted and published some of the best quality measurements in 
> the industry.  Our measurements fully correlate to:  First physical 
> principles, simulation using multiple tools, and in-system evaluations.  
> Our measurements repeatedly contradict your claims.  We repeatedly offer 
> to work with you to prove to you at any level of scientific satisfaction 
> why our results are correct and what is wrong with your fixtures and 
> methods.  Time and time again you have decline to take us up on our 
> offers.  Time and time again you fail to show any fault with our 
> methods.  You challenge completely on the basis that your results taken 
> from demonstrably deficient test vehicles are different.  I am sorry, 
> but clinging to conclusions drawn from known faulty methods, while 
> ignoring well-vetted experiments is just bad science.
>
> With respect to "Comparison of X2Y vs. 0402 Capacitors for Decoupling", 
> the old adage "Garbage in => garbage out" aptly applies.  John skewed 
> his results by:
>
> 1) Choosing extremely aggressive via and land pattern for the 0402 case, 
> and a deplorably bad via and land pattern for the X2Y(r) case. 
> 2) Using a vehicle that is ill designed to either extract individual 
> device performance, or function as a system analog.
>
> The land patterns-
> As depicted in the photographs on page 3 of that piece, John's 0402 via 
> annular rings encroach the capacitor pad with no clearance for a solder 
> mask dam.  In the same set of photogrpahs, John extended the X2Y(r) vias 
> both far away from the capacitor body and each other with skinny 
> inductive traces.  The vias are spaced so far apart that five X2Y(r) 
> components can be fitted within John's horrific via pattern.  The test 
> board photograph on page 4 provides a striking view of that layout, 
> where it is readily visible that the 0603 X2Y(r) layout it is comparable 
> in size to the 0612 reverse geometry layout.  Since John is clearly 
> aware that a bad via / land pattern can hobble the performance of any 
> capacitor, it is only fair to ask why he elected to employ such an awful 
> pattern when evaluating X2Y(r).  Even if the gross misdesign was just a 
> mistake at the time, I identified the problems to you when I first saw 
> this report in late 2005.  Since then, rather than fix the problems you 
> instead insist these garbage results are valid.  As a responsible 
> practitioner, how do you justify such obviously warped results that have 
> been directly and repeatedly contradicted by well-documented hard
science? 
>
> The test vehicle design-
> If the intent is to extract the inductance of a single capacitor, it is 
> important to construct a vehicle where the device inductance is clearly 
> visible and fixture spatial effects are readily deembedded.  Near each 
> the SRF and the PRF, capacitance of the DUT in the former, and DUT plus 
> distributed test fixture capacitance for the latter strongly impact 
> measurements.  John's choice of DUT capacitor values, combined with 
> large fixture capacitance result in SRFs and PRFs separated by a only 
> one to two octaves.  The result is a lot of coloration by the fixture 
> that is very difficult to deembed.  The really bad news is that the 
> deembedding problems make high inductance capacitors appear to perform 
> better than they really do.  Contrast this to fixtures such as we have 
> developed that separate the SRF and PRFs by seven octaves or more.  In 
> those cases the inductance of the DUTs is readily extractable.  The 
> resulting mounted inductance numbers for all types of capacitors 
> characterized are reliable.
>
> If we want an analog of an actual power system, it is important to 
> replicate the areal density of bypass capacitors that will be used in 
> the system being modeled, as well as to replicate noise injection and 
> measurement that is faithful to the intended application.  Again:  
> John's fixture fails on both accounts.  The capacitor density of any 
> kind is very low compared to any real system, resulting in the low PRFs, 
> and high impedance even for such a small PCB. As depicted in John's 
> impedance plots, the evaluated configurations are below an ohm only over 
> little more than a decade from about 8MHz to 100MHz for the V5 cavity 
> and about 180MHz for the V1 cavity.  Further, the capacitor 
> distributions with respect to the RF injection and monitor points are 
> highly varied as are the locations with respect to the PCB boundaries.  
> You could find this either by reproducing the vehicle with different 
> test site locations, and/or modeling in any of a number of tools.  As a 
> result, the measurements do not reflect what an IC connected to any real 
> power system would see.
>
> Anyone who wishes can reproduce our measurements.  All it takes is the: 
> time, equipment, patience, and will to do so. 
>
> The Teraspeed(r) web site also has a number of papers on power delivery 
> and bypassing:  http://www.teraspeed.com
> The X2Y(r) web includes many of those papers as well as many X2Y(r) 
> specific papers:  http://www.x2y.com/bypass.
>
> A good paper to start with is:  "Understanding Capacitor Inductance and 
> Measurement in Power Bypass Applications"  
> http://www.x2y.com/bypass/measure/understand_cap_inductance.pdf
>
> A good reference for proper mounting of X2Y(r) capacitors is:  
> http://www.x2y.com/bypass/mount/get_the_most.pdf   In that report you 
> will see what we mean by superior physical design.  Whereas John 
> believes he is yielding 480pH w/ 0402s using 4 via attachments, we show 
> practical stack-ups and X2Y(r) attachments that yield 120pH using six 
> vias.  To get the same performance John would have to drill sixteen 
> route blocking vias and place four capacitors.
>
> An critique on John's article is available:  
> http://www.x2y.com/publications/decoupling/csrbt.pdf
>
> Steve.
>
> Lee Ritchey wrote:
> > Guess it's time to cut through the discusson and make some measurements.
> >
> > On my web site, www.speedingedge.com, is a paper titled "Comparison of
X2Y
> > vs. 0402 Capacitors for Decoupling" authored by John Zasio.  There is a
> > common test vehicle, the X2Y and the 0402 capacitors being tested are
> > mounted on the same PCB using the manufacturer recommended mounting for
the
> > X2Y capacitor and a 4 via mounting for the 0402 capacitor.  The test
setup
> > is identical for both capacitors, so the differences in measurements
should
> > be only those associated with each capacitor.  The test method is one
> > commonly used in the industry to measure PDS Z vs. F, namely a spectrum
> > analyser with a tracking signal generator.
> >
> > The results speak for themselves.  There is only a slight difference in
the
> > performance of the two capacitors suggesting that either the  0402 is a
> > magically very good capacitor- as good as an X2Y or that the X2Y is
about
> > the same as an 0402.  The readers can decide for themselves which is the
> > accurate interpretation.
> >
> > My conclusion, along with many others in the industry, is that the X2Y
has
> > similar mouning inductance to an 0402 when used on a multilayer PCB. 
The
> > same can be said for an IDC capacitor.  The IDC measurements are in our
> > book.
> >
> > If those who argue otherwise want to debunk this set of measurements,
it is
> > incumbent on them to measure the two styles of capacitors under
indentical
> > conditions and post their results.
> >
> > Lee Ritchey
> > Speeding Edge
> >
> >   
> >> [Original Message]
> >> From: Scott McMorrow <scott@xxxxxxxxxxxxx>
> >> To: Lee Ritchey <leeritchey@xxxxxxxxxxxxx>
> >> Cc: Steve Weir <weirsi@xxxxxxxxxx>; QU Perry
> >>     
> > <Perry.Qu@xxxxxxxxxxxxxxxxxx>; <si-list@xxxxxxxxxxxxx>
> >   
> >> Date: 2/26/2008 7:19:08 AM
> >> Subject: [SI-LIST] Re: [!! SPAM]  Re: 6 layers stackup
> >>
> >> Lee
> >> I apologize for misinterpreting your calculation of capacitor 
> >> inductance.  However, your numbers still do not hold.  Lets take a
board 
> >> where the planes are 40 mils down with a via inductance of 17.5 pH/mil 
> >> per via pair for 0402 capacitors and 5 pH/mil per 6 via mount for X2Y 
> >> capacitor.
> >>
> >> 40 mil case
> >> Via attach inductance = 17.5 pH/mil x 40 = 700 pH
> >> 0402 capacitor inductance = 450 pH
> >> total inductance 0402 capacitor = 1.15 nH
> >>
> >> X2Y capacitor via attach inductance = 5 pH/mil x 40 = 200 pH
> >> X2Y capacitor inductance = 120 pH
> >> total inductance X2Y capacitance = 320 pH
> >>
> >> Inductance ratio  0402 vs. X2Y = 1150/320 = 3.59:1 (planes 40 mils
down)
> >>
> >> If we perform the same calculations with the planes 20 mils down, we
get:
> >>
> >> Total inductance 0402 capacitor = 800 pH
> >> Total inductance X2Y capacitor = 220 pH
> >> Inductance ratio 0402 vs. X2Y = 3.64:1
> >>
> >> By virtue of the fact that low inductance capacitors utilize multiple 
> >> vias that take advantage of mutual inductance coupling, there are 
> >> inherent inductance advantages in the body of the capacitor itself and 
> >> within the coupled via system that penetrates the planes.  For
example, 
> >> if you look at an X2Y capacitor via pattern you will see that although 
> >> there are 6 vias used, there are 4 well-coupled via pairs.  This 
> >> provides lower overall inductance than what would be provided by 3
sets 
> >> of spatially isolated via pairs, as is the case with 0402 capacitor 
> >> mounting patterns.
> >>
> >> No matter how we cut it, simulate it, or measure it, a well-mounted
X2Y 
> >> capacitor has better than 3:1 performance advantage over an 0402 
> >> capacitor.   It's not magic, it's science.
> >>
> >>
> >> Regards,
> >>
> >> Scott
> >>
> >> Scott McMorrow
> >> Teraspeed Consulting Group LLC
> >> 121 North River Drive
> >> Narragansett, RI 02882
> >> (401) 284-1827 Business
> >> (401) 284-1840 Fax
> >>
> >> http://www.teraspeed.com
> >>
> >> Teraspeed® is the registered service mark of
> >> Teraspeed Consulting Group LLC
> >>
> >>
> >>
> >> Lee Ritchey wrote:
> >>     
> >>> I disagree that ultralow inductance capacitors perform significantly
> >>>       
> > better
> >   
> >>> that standard two leaded capacitors such as 0402 and 0603 due to the
> >>>       
> > added
> >   
> >>> inductance associated with the mounting pads and mounting vias.  This
> >>>       
> > has
> >   
> >>> been supported many times by physical measurements on real PCBs and is
> >>> documented in my book, "Right the First Time, A Practical Handbook on
> >>>       
> > High
> >   
> >>> Speed PCB and Systetm Design" as well as in several other sources.
> >>>
> >>> I am mystified at how it can be claimed that this is not so when the
> >>> inductance of the vias connecting capacitors to the associated planes
> >>> averages something like 35 pH per mil of length- no matter what  kind
of
> >>> magical capacitor they are connected to.  It is especially true when
> >>>       
> > one is
> >   
> >>> speaking of a six layer PCB that has planes 20-40 mils below the
> >>>       
> > surface. 
> >   
> >>> That is 0.7 nH to 1.4 nH per lead.  Even if the capacitor has 0.1 nH
> >>> inductance as an IDC capacitor is said to have, the total inductance
is
> >>> driven up near 1 nH.  How can any capacitor make this go away?
> >>>
> >>> It is time to stop pretending that there are magic capacitors out
there.
> >>>
> >>> Lee Ritchey
> >>> Speeding Edge.
> >>>
> >>>
> >>>   
> >>>       
> >>>> [Original Message]
> >>>> From: steve weir <weirsi@xxxxxxxxxx>
> >>>> To: QU Perry <Perry.Qu@xxxxxxxxxxxxxxxxxx>
> >>>> Cc: <si-list@xxxxxxxxxxxxx>
> >>>> Date: 2/25/2008 11:52:30 AM
> >>>> Subject: [SI-LIST] Re: 6 layers stackup
> >>>>
> >>>> Perry, the discussion has been limited to 4/6 layer boards with a
> >>>>         
> > single 
> >   
> >>>> symmetric power cavity.  The Z axis inductance for an IC or bypass
cap 
> >>>> to the cavity depends on the distance to the center of the cavity. 
> >>>>         
> > With 
> >   
> >>>> a single, symmetric cavity, that is going to be half the board 
> >>>> thickness.  This is not to be confused with higher layer count
boards 
> >>>> where we can place at least one modestly thin cavity near the IC / 
> >>>> capacitor mounting surface.  In all cases, the cavity spreading 
> >>>> inductance becomes a limiting factor in PDN impedance.  Cavity
> >>>>         
> > impedance 
> >   
> >>>> varies directly with cavity height.
> >>>>
> >>>> In the case of any almost thickness PCB, the via attachment structure
> >>>>         
> > is 
> >   
> >>>> a significant, if not dominant contributor to the mounted capacitor 
> >>>> inductance, that is the inductance as seen at that attachment point
at 
> >>>> the planes.  Capacitors like X2Y(r)'s, and IDC(r)'s when properly 
> >>>> attached yield much lower inductance than discrete caps.  This is 
> >>>> readily modeled in any number of tools, and confirmed by properly 
> >>>> constructed experiments.  So low inductance caps still work, whether
> >>>>         
> > or 
> >   
> >>>> not you have a thin cavity, and whether or not the cavity is adjacent
> >>>>         
> > to 
> >   
> >>>> the caps.
> >>>>
> >>>> We are talking about two different resonances.  The resonance that
you 
> >>>> are referring to are the half-wave modes.  I am talking about the 
> >>>> parallel resonance between the bypass network and the power cavity.  
> >>>> This is the beast that eats most people's lunch.  It is a matter of 
> >>>> capacitance per unit area of the cavity which depends directly on 
> >>>> height, and the area / unit inductance of the bypass network.
> >>>>
> >>>> Best Regards,
> >>>>
> >>>>
> >>>> Steve.
> >>>>
> >>>> QU Perry wrote:
> >>>>     
> >>>>         
> >>>>> Steve:
> >>>>>
> >>>>> My understanding on the impact of thinner power cavity is mainly the
> >>>>> reduction of spread inductance, such that any added benefit of
IDC/X2Y
> >>>>> placed at the peripheral of BGA will not be compromised by the
> >>>>>           
> > planes..
> >   
> >>>>> In most applications however, we rely heavily on the decoupling caps
> >>>>> (0402) directly placed underneath BGAs, and in those cases, I would
> >>>>> think thickness of power cavity is not important as the total
> >>>>>           
> > inductance
> >   
> >>>>> looking into PCB from BGA pads to the planes and to the decoupling
> >>>>>           
> > caps
> >   
> >>>>> don't change. Your thoughts ?
> >>>>>
> >>>>> I'm also not clear when you say parallel resonance frequency is
driven
> >>>>> by thickness. Comparing Z dimension vs. X/Y for a normal power
> >>>>>           
> > plane/PCB
> >   
> >>>>> thickness, I would say the resonance frequency is mainly determined
by
> >>>>> how big the plane is not how thick the cavity ?
> >>>>>
> >>>>> Thanks
> >>>>>
> >>>>> Perry
> >>>>>
> >>>>> ======================================= 
> >>>>>
> >>>>> Perry Qu 
> >>>>>
> >>>>> Design & Qualification, Alcatel-Lucent Canada Inc.
> >>>>>
> >>>>> 600 March Road, Ottawa ON, K2K 2E6, Canada 
> >>>>>
> >>>>> DID: 613-7846720  Fax: 613-5993642 
> >>>>>
> >>>>> Email: perry.qu@xxxxxxxxxxxxxxxxxx 
> >>>>>
> >>>>> ======================================= 
> >>>>>
> >>>>>  
> >>>>>
> >>>>>   
> >>>>>       
> >>>>>           
> >>>>>> -----Original Message-----
> >>>>>> From: si-list-bounce@xxxxxxxxxxxxx 
> >>>>>> [mailto:si-list-bounce@xxxxxxxxxxxxx] On Behalf Of steve weir
> >>>>>> Sent: Saturday, February 23, 2008 6:44 PM
> >>>>>> To: DAVID CUTHBERT
> >>>>>> Cc: Fernando Yuitiro Mori; si-list@xxxxxxxxxxxxx
> >>>>>> Subject: [SI-LIST] Re: 6 layers stackup
> >>>>>>
> >>>>>> Dave, Fernando my $0.02 on 4/6 layer stack-ups with a single 
> >>>>>> symmetric power cavity:
> >>>>>>
> >>>>>> 1) The Z-axis inductance seen at the IC solder pads to the 
> >>>>>> power cavity is pretty much fixed by:
> >>>>>>
> >>>>>> a. The total thickness of the PCB.
> >>>>>> b. The pin-out of the IC.
> >>>>>> c. The via drill diameter.
> >>>>>>
> >>>>>> 2) Similarly the Z-axis inductance seen between the bypass 
> >>>>>> caps and the power cavity is fixed by:
> >>>>>>
> >>>>>> a. The total thickness of the PCB.
> >>>>>> b. The type of bypass capacitors used.
> >>>>>> c. The via pattern used w/ the bypass caps.
> >>>>>> d. The via drill diameter.
> >>>>>> e. The areal density of the bypass caps used.
> >>>>>>
> >>>>>> b/c/d Determine the mounted inductance of each cap.  X2Y(r)'s 
> >>>>>> and IDC(r)'s yield the best results.  In all cases the via 
> >>>>>> pattern used makes a big difference in the number of caps 
> >>>>>> used and the behavior at parallel resonance.  In my mind it 
> >>>>>> is a lot better to floor plan bypass caps w/ optimal via 
> >>>>>> patterns up front, than to have the PCB designer try to fit 
> >>>>>> them in later.
> >>>>>>
> >>>>>> 3) As the power cavity is made thinner, six notable things happen:
> >>>>>>
> >>>>>> a. The horizontal spreading inductance of the planes falls.  
> >>>>>> The extremes for six layer 0.062" stack-ups can be almost 
> >>>>>> 10:1 going from a
> >>>>>> 4 mil to a 38 mil power core.
> >>>>>> b. The high frequency impedance of the power system comes 
> >>>>>> down.  On the bad side one will be in PCB wave effects at 
> >>>>>> lower frequencies.  Detuning w/ discretes takes about the 
> >>>>>> same number of parts independent of the cavity thickness.  
> >>>>>> Tolerances are more forgiving for the thinner cavity.
> >>>>>> c. The parallel resonant frequency of the power system comes 
> >>>>>> down as the square root of the power cavity thickness.  
> >>>>>> Typical resonant frequencies typically vary over a 300MHz to 
> >>>>>> 1.5GHz range depending on bypass scheme over the 4mil to 
> >>>>>> 38mil cavity thicknesses.
> >>>>>> d. The Q of the parallel resonance goes up.  On the good 
> >>>>>> side, higher Qs 
> >>>>>> are generally easier to detune.   The bad side is that the natural 
> >>>>>> magnitude of Zpeak is fairly independent of the cavity 
> >>>>>> thickness, now it is much more likely to be where there is 
> >>>>>> more signal energy.  The moral here is:  detune the resonance.
> >>>>>> e. Above and below the resonant frequency noise attenuation
> >>>>>>             
> > improves..
> >   
> >>>>>> f. The asymmetry between outer and inner routing layers in a 
> >>>>>> 6 layer stack-up become more pronounced and routing density 
> >>>>>> can suffer severely.  Maintaining 50Ohms and/or acceptable 
> >>>>>> cross talk values on outer layers more than about 10 mils 
> >>>>>> from an image plane demands some rather wide traces and 
> >>>>>> routing pitches.
> >>>>>>
> >>>>>> 4) An S1 G S2 S3 P S4 stack-up works best when the highest 
> >>>>>> speed signals can be broken out and routed completely on S1.  
> >>>>>> Otherwise S1 P S2 S3 G
> >>>>>> S4 is usually better breaking out high speed signals on layer 
> >>>>>> S4 first and layer S3 second, minimizing via stubs.  In 
> >>>>>> either case prioritizing the traces with the most high speed 
> >>>>>> energy to the routing layer(s) adjacent an image plane 
> >>>>>> connected to the dominant coupling rail in the IC will help 
> >>>>>> reduce demands on the PDN.  That rail is usually ground.
> >>>>>>
> >>>>>> Best Regards,
> >>>>>>
> >>>>>> Steve.
> >>>>>>
> >>>>>>
> >>>>>> DAVID CUTHBERT wrote:
> >>>>>>     
> >>>>>>         
> >>>>>>             
> >>>>>>> Fernando,
> >>>>>>> The S1 S2 G P S3 S4 stackup can provide excellent power plane 
> >>>>>>> performance at the expense of S1 and S4. Routing S1 and S4 
> >>>>>>>       
> >>>>>>>           
> >>>>>>>               
> >>>>>> mostly at 
> >>>>>>     
> >>>>>>         
> >>>>>>             
> >>>>>>> right angles to S2 and
> >>>>>>> S3 can greatly reduce the crosstalk. And using narrow traces to 
> >>>>>>> maintain the Z0 of S1 and S4 will take care of the Z0.
> >>>>>>>
> >>>>>>> I often use S1 G S2 -  S3 P S4 for 6-layer boards. The 
> >>>>>>>       
> >>>>>>>           
> >>>>>>>               
> >>>>>> signal traces 
> >>>>>>     
> >>>>>>         
> >>>>>>             
> >>>>>>> are nicely isolated with a 62 mil board having spacing like so:
> >>>>>>> 10 mils, 5 mils, 22 mils, 5 mils, 10 mils. The tradeoff is that
the 
> >>>>>>> power plane Z0 is about 2X that of a board having 10 mils 
> >>>>>>>       
> >>>>>>>           
> >>>>>>>               
> >>>>>> between each 
> >>>>>>     
> >>>>>>         
> >>>>>>             
> >>>>>>> layer. The power plane Z0 is still quite low with an inductance
of 
> >>>>>>> about 200 pH per square. Contrast this to an S1-G via inductance
of 
> >>>>>>> about 300 pH and the plane Z does not dominate things.
> >>>>>>>
> >>>>>>>      Dave Cuthbert
> >>>>>>>      NARTE Certified EMC Engineer
> >>>>>>>      Consulting, SI, EMC, power electronics, analog of all kinds
> >>>>>>>
> >>>>>>>
> >>>>>>> On Wed, Feb 20, 2008 at 2:17 PM, Fernando Yuitiro Mori 
> >>>>>>> <mori@xxxxxxxxxxxxx>
> >>>>>>> wrote:
> >>>>>>>
> >>>>>>>   
> >>>>>>>       
> >>>>>>>           
> >>>>>>>               
> >>>>>>>> Hi,
> >>>>>>>> I normally use S1 S2 G P S3 S4 for the 6 layers stackup. I 
> >>>>>>>>         
> >>>>>>>>             
> >>>>>>>>                 
> >>>>>> need the 4 
> >>>>>>     
> >>>>>>         
> >>>>>>             
> >>>>>>>> layer with 60 ohms, so there are some problem if I use S1 
> >>>>>>>>         
> >>>>>>>>             
> >>>>>>>>                 
> >>>>>> G S2 S3 P S4?
> >>>>>>     
> >>>>>>         
> >>>>>>             
> >>>>>>>> Regards,
> >>>>>>>>
> >>>>>>>> Fernando Mori
> >>>>>>>>
------------------------------------------------------------------
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> >>>>>>>   
> >>>>>>>
> >>>>>>>
> >>>>>>>   
> >>>>>>>       
> >>>>>>>           
> >>>>>>>               
> >>>>>> --
> >>>>>> Steve Weir
> >>>>>> Teraspeed Consulting Group LLC
> >>>>>> 121 North River Drive
> >>>>>> Narragansett, RI 02882 
> >>>>>>
> >>>>>> California office
> >>>>>> (408) 884-3985 Business
> >>>>>> (707) 780-1951 Fax
> >>>>>>
> >>>>>> Main office
> >>>>>> (401) 284-1827 Business
> >>>>>> (401) 284-1840 Fax 
> >>>>>>
> >>>>>> Oregon office
> >>>>>> (503) 430-1065 Business
> >>>>>> (503) 430-1285 Fax
> >>>>>>
> >>>>>> http://www.teraspeed.com
> >>>>>> This e-mail contains proprietary and confidential 
> >>>>>> intellectual property of Teraspeed Consulting Group LLC
> >>>>>> --------------------------------------------------------------
> >>>>>> ----------------------------------------
> >>>>>> Teraspeed(R) is the registered service mark of Teraspeed 
> >>>>>> Consulting Group LLC
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> >>>>>>
> >>>>>>
> >>>>>> List technical documents are available at:
> >>>>>>                 http://www.si-list.net
> >>>>>>
> >>>>>> List archives are viewable at:     
> >>>>>>                http://www.freelists.org/archives/si-list
> >>>>>> or at our remote archives:
> >>>>>>                http://groups.yahoo.com/group/si-list/messages
> >>>>>> Old (prior to June 6, 2001) list archives are viewable at:
> >>>>>>                http://www.qsl.net/wb6tpu
> >>>>>>   
> >>>>>>
> >>>>>>
> >>>>>>     
> >>>>>>         
> >>>>>>             
> >>>>>   
> >>>>>       
> >>>>>           
> >>>> -- 
> >>>> Steve Weir
> >>>> Teraspeed Consulting Group LLC 
> >>>> 121 North River Drive 
> >>>> Narragansett, RI 02882 
> >>>>
> >>>> California office
> >>>> (408) 884-3985 Business
> >>>> (707) 780-1951 Fax
> >>>>
> >>>> Main office
> >>>> (401) 284-1827 Business 
> >>>> (401) 284-1840 Fax 
> >>>>
> >>>> Oregon office
> >>>> (503) 430-1065 Business
> >>>> (503) 430-1285 Fax
> >>>>
> >>>> http://www.teraspeed.com
> >>>> This e-mail contains proprietary and confidential intellectual
property
> >>>>     
> >>>>         
> >>> of Teraspeed Consulting Group LLC
> >>>   
> >>>
> >>>       
> >
----------------------------------------------------------------------------
> >   
> >>> --------------------------
> >>>   
> >>>       
> >>>> Teraspeed(R) is the registered service mark of Teraspeed Consulting
> >>>>         
> > Group
> >   
> >>>>     
> >>>>         
> >>> LLC
> >>>   
> >>>       
> >>>> ------------------------------------------------------------------
> >>>> To unsubscribe from si-list:
> >>>> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >>>>
> >>>> or to administer your membership from a web page, go to:
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> >>>>
> >>>> For help:
> >>>> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >>>>
> >>>>
> >>>> List technical documents are available at:
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> >>>> or at our remote archives:
> >>>>          http://groups.yahoo.com/group/si-list/messages
> >>>> Old (prior to June 6, 2001) list archives are viewable at:
> >>>>                  http://www.qsl.net/wb6tpu
> >>>>   
> >>>>     
> >>>>         
> >>> ------------------------------------------------------------------
> >>> To unsubscribe from si-list:
> >>> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >>>
> >>> or to administer your membership from a web page, go to:
> >>> http://www.freelists.org/webpage/si-list
> >>>
> >>> For help:
> >>> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >>>
> >>>
> >>> List technical documents are available at:
> >>>                 http://www.si-list.net
> >>>
> >>> List archives are viewable at:     
> >>>           http://www.freelists.org/archives/si-list
> >>> or at our remote archives:
> >>>           http://groups.yahoo.com/group/si-list/messages
> >>> Old (prior to June 6, 2001) list archives are viewable at:
> >>>           http://www.qsl.net/wb6tpu
> >>>   
> >>>
> >>>
> >>>   
> >>>       
> >> ------------------------------------------------------------------
> >> To unsubscribe from si-list:
> >> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
> >>
> >> or to administer your membership from a web page, go to:
> >> http://www.freelists.org/webpage/si-list
> >>
> >> For help:
> >> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
> >>
> >>
> >> List technical documents are available at:
> >>                 http://www.si-list.net
> >>
> >> List archives are viewable at:     
> >>            http://www.freelists.org/archives/si-list
> >> or at our remote archives:
> >>            http://groups.yahoo.com/group/si-list/messages
> >> Old (prior to June 6, 2001) list archives are viewable at:
> >>            http://www.qsl.net/wb6tpu
> >>   
> >>     
> >
> >
> >
> >   
>
>
> -- 
> Steve Weir
> Teraspeed Consulting Group LLC 
> 121 North River Drive 
> Narragansett, RI 02882 
>
> California office
> (408) 884-3985 Business
> (707) 780-1951 Fax
>
> Main office
> (401) 284-1827 Business 
> (401) 284-1840 Fax 
>
> Oregon office
> (503) 430-1065 Business
> (503) 430-1285 Fax
>
> http://www.teraspeed.com
> This e-mail contains proprietary and confidential intellectual property
of Teraspeed Consulting Group LLC
>
----------------------------------------------------------------------------
--------------------------
> Teraspeed(R) is the registered service mark of Teraspeed Consulting Group
LLC
>
> ------------------------------------------------------------------
> To unsubscribe from si-list:
> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>
> or to administer your membership from a web page, go to:
> http://www.freelists.org/webpage/si-list
>
> For help:
> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>
>
> List technical documents are available at:
>                 http://www.si-list.net
>
> List archives are viewable at:     
>               http://www.freelists.org/archives/si-list
> or at our remote archives:
>               http://groups.yahoo.com/group/si-list/messages
> Old (prior to June 6, 2001) list archives are viewable at:
>               http://www.qsl.net/wb6tpu
>   


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field


List technical documents are available at:
                http://www.si-list.net

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  

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