[SI-LIST] Re: [!! SPAM] Re: 6 layers stackup

All,

I do not think John's paper was skewed any more than other papers I have
seen on this topic. His paper illustrates that capacitors mounted with
similar via structure inductances exhibit similar performance. An apples
to apples comparison between X2Y caps and two-terminal caps is difficult
because the X2Y terminal structure lends itself to a 6-via mounting
configuration that is difficult to achieve with a single 0402 cap.
Nevertheless, two-terminal caps can be mounted much more effectively
than they are in the papers that show X2Y caps performing 2 to 3 times
better.

The inductance associated with the internal construction of the
capacitor is only going to be a relevant factor when the capacitor is
mounted on (or embedded in) the planes. Even in this situation, some
two-terminal designs look pretty good and the details of the mounting
structure can be more important than the type of capacitor used. =20

Todd Hubing
Clemson University Vehicular Electronics Laboratory
http://www.cvel.clemson.edu/ =20


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of steve weir
Sent: Tuesday, February 26, 2008 11:08 PM
To: Tom Biggs
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup

Tom, I am full agreement with Lee that data sheet "capacitor only"=20
inductance values are not useful for bypass applications.  For power=20
bypass, designers need to know what the inductance is of the combined=20
capacitor and attachment structure to the plane cavity: wherever that=20
may be.  The "bulldozer" here is not the length of the vias, but the=20
combination of lightly loaded cavities and test fixtures that are not=20
deembedded.  Lee and John's good intention was to measure actual=20
attached capacitor performance.  For the reasons stated in my earlier=20
message, the test fixture is not suitable to doing that with any good=20
accuracy.  Further, John's choice of an absolutely ridiculous via and=20
surface connection pattern for the X2Y(r) cap severely skewed their=20
results.

The bone of contention is that Lee professes the belief that low=20
inductance caps get hobbled by vias to the extent that their replacement

ratio over regular caps doesn't hold in a conventional PCB.  We have=20
proven that belief false for any well-designed via attachment pattern. =20
More importantly, we have proven that the impact of via length: that is=20
the total inductance added per unit length multiplied by the number of=20
vias used is substantially better with X2Y(r) caps than it is with=20
conventional 0402s.  What that means is that to get to a given=20
inductance target, the replacement ratio of X2Y(r) type capacitors to=20
conventional 0402s does not significantly degrade with distance from the

capacitor mounting surface to the attached cavity.   At any inductance=20
target, and for any distance from the capacitor surface to the power=20
cavity, X2Y(r) capacitors require fewer total vias than conventional=20
0402 or 0603 capacitors.  Charts for attached inductance versus cavity=20
depth for various types of capacitors including X2Y(r)s can be found in=20
application notes on the X2Y(r) web site:  www.x2y.com/bypass.htm.

In order to fix Lee's fixture, he needs to do a couple of things:=20

1) Fix the areal density of capacitors to be representative of intended=20
design practice.  This will fix the impedance and PRF.
2) Device a way to deembed his fixture from the what he is measuring.

I have no doubt that once that is done, Lee will obtain the same or very

similar results to those that we report.

Best Regards,


Steve.

Tom Biggs wrote:
> You can take the bulldozer analogy two ways. It depends on whether you
> care about the weight of the bulldozer with passengers, or just the
> weight of the passengers.
>
> Steve's test fixture was geared toward 'weighing the passengers'.
Lee's
> was toward 'weighing the bulldozer'. So they each served their
purpose.
> His whole point was that the vias going down 50 mils on a board are
> going to swamp out the advantages of low inductance caps. His test
> fixture, by design, had vias that go down 50mils. I'm sure he'd agree
> that this would be a bad fixture for measuring the cap itself, which
was
> not his goal.
>
> The appropriate land pattern to use for the low-inductance caps is a
> separate issue. I'd be curious to see Lee's board with Steve's land
> pattern.
>
>     -tom
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Muranyi, Arpad
> Sent: Tuesday, February 26, 2008 1:31 PM
> To: si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup
>
> Can't resist to illustrate this with an example:
>
> If you want to compare the weight of an ant and a cricket and you put
> them on top of the same bulldozer, you will not see much difference in
> their weight...
>
> Arpad
>
------------------------------------------------------------------------
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx
[mailto:si-list-bounce@xxxxxxxxxxxxx]
> On Behalf Of Lee Ritchey
> Sent: Tuesday, February 26, 2008 11:16 AM
> To: Charles Grasso; Scott McMorrow
> Cc: Steve Weir; QU Perry; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup
>
> What does the test vehicle have to do with it?  Both capacitors are
> seeing
> the same stackup.  It's apples and apples.   Why 26 layers?  Lots of
> PCBs
> have 26 layers, pretty much all of them in terabit routers.  This PCB
> was used to test may things besides these two capacitors.
>
> What is being presented is the difference between the two capacitors
> under the same set of test conditions and it is not much.
>
> There are two sets of tests.  One with the capacitors connected to the
> first two planes inside the PCB, which is the lowest added inductance
> and the other is with the capacitors attached to two planes further
down
> in the PCB.
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--=20
Steve Weir
Teraspeed Consulting Group LLC=20
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