[SI-LIST] Re: [SI-LIST]6 layers stackup - proof

All,
The howard johnson video had one fundamental flaw in how he (and steve) came to 
their conlusion.  This flaw was that the 0402 caps vs. the x2y caps were not 
apples to apples comparisons.  Why?  The reason is comparing 0402 cpacitors of 
220nf with x2y caps of 100nf are not the same thing!  Sure, two 100nf caps in 
parallel equate to 200nf (which is what dr. johnson stated in the video as to 
why they are the same thing) but I challenge anyone to perform a noise 
experiment where you have 1 200nf cap vs. 2 100nf caps and try and get the same 
noise measurement.  The resonance frequency of 200nf is about 16mhz and the 
resonance frequency of the 100nf is about 25mhz.  thus the impedance due to 
these capacitors above 20mhz is greater for the 200nf case - this is just 
fundamental capacitor science.  This is exactly what happened in howard 
johnsons video.  This is not rocket science just basic ohms-law.  All this 
gobbly-gook talk of via incuctance, etc. is in the small noise (no pun 
intended) of why the results in that video differed.  See attachement.

Dan



-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On 
Behalf Of Scott McMorrow
Sent: Wednesday, February 27, 2008 9:34 AM
To: Lee Ritchey
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [SI-LIST]6 layers stackup

Lee
Fortunately for us, the physics are clear.  If the correct land/via
patterns are used, 50 mils of via reach will not swamp out the
advantages of some types of low inductance capacitors.  In fact, the
difference will asymptotically approach the inductance ratio of the
coupled via systems themselves at infinite via length.

For the case of X2Y capacitors with 6-vias vs. 0402 with 4-vias, this
ratio is 2:1.  That is, the 6-via pattern of the X2Y is 2 times as
efficient as the 4-via 0402 pattern.  Even if we normalize for number of
vias, the X2Y pattern is still 1.33 times more efficient per via drill.
However, in real PCBs we are not dealing with infinitely long vias, so
the performance advantage is much better, and typically 3:1 or 4:1
depending on the 0402 via pattern (2-via or 4-via) used.

However, if you incorrectly design your board such that a PRF occurs
within a few octaves of where you need low PDS impedance, that is a
different issue altogether, which can only be resolved by moving the PRF
with the correct spatial distribution of capacitors.  Low inductance
capacitors are also more efficient in dealing with this problem.


Scott

Scott McMorrow
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
(401) 284-1827 Business
(401) 284-1840 Fax

http://www.teraspeed.com

Teraspeed(r) is the registered service mark of
Teraspeed Consulting Group LLC



Lee Ritchey wrote:
> Tom,
>
> Well put!
>
>
>
>> [Original Message]
>> From: Tom Biggs <tbiggs@xxxxxxxxxxxxxxxxxxxxx>
>> To: <si-list@xxxxxxxxxxxxx>
>> Date: 2/26/2008 6:16:04 PM
>> Subject: [SI-LIST] Re: [!! SPAM]  Re: 6 layers stackup
>>
>> You can take the bulldozer analogy two ways. It depends on whether you
>> care about the weight of the bulldozer with passengers, or just the
>> weight of the passengers.
>>
>> Steve's test fixture was geared toward 'weighing the passengers'. Lee's
>> was toward 'weighing the bulldozer'. So they each served their purpose.
>> His whole point was that the vias going down 50 mils on a board are
>> going to swamp out the advantages of low inductance caps. His test
>> fixture, by design, had vias that go down 50mils. I'm sure he'd agree
>> that this would be a bad fixture for measuring the cap itself, which was
>> not his goal.
>>
>> The appropriate land pattern to use for the low-inductance caps is a
>> separate issue. I'd be curious to see Lee's board with Steve's land
>> pattern.
>>
>>     -tom
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Muranyi, Arpad
>> Sent: Tuesday, February 26, 2008 1:31 PM
>> To: si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup
>>
>> Can't resist to illustrate this with an example:
>>
>> If you want to compare the weight of an ant and a cricket and you put
>> them on top of the same bulldozer, you will not see much difference in
>> their weight...
>>
>> Arpad
>> ------------------------------------------------------------------------
>>
>> -----Original Message-----
>> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>> On Behalf Of Lee Ritchey
>> Sent: Tuesday, February 26, 2008 11:16 AM
>> To: Charles Grasso; Scott McMorrow
>> Cc: Steve Weir; QU Perry; si-list@xxxxxxxxxxxxx
>> Subject: [SI-LIST] Re: [!! SPAM] Re: 6 layers stackup
>>
>> What does the test vehicle have to do with it?  Both capacitors are
>> seeing
>> the same stackup.  It's apples and apples.   Why 26 layers?  Lots of
>> PCBs
>> have 26 layers, pretty much all of them in terabit routers.  This PCB
>> was used to test may things besides these two capacitors.
>>
>> What is being presented is the difference between the two capacitors
>> under the same set of test conditions and it is not much.
>>
>> There are two sets of tests.  One with the capacitors connected to the
>> first two planes inside the PCB, which is the lowest added inductance
>> and the other is with the capacitors attached to two planes further down
>> in the PCB.
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