[SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc ussion

Those nasty lossy return paths do make things a little more difficult.
Analytically.. and empirically...

ap


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On
Behalf Of Chris Cheng
Sent: Thursday, April 29, 2004 6:01 PM
To: 'Jon Powell'; arpad.muranyi@xxxxxxxxx; Chris Cheng;
si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc =
ussion


Arpad and Jon,

I tell you what. Talk is cheap, go back to the original circa '93 GTL
circuit paper Bill Gunning published in ISSCC or my first paper on GTL
system in Hot Interconnect where the full driver circuit is detailed and =
the
measured SSO delay and switching noise were also published. Use your =
best
IBIS/behavioral model tool NOW and see if it can generate the same
asymmetric SSO delay and switching noise under the system load and let's =
see
if you can run 100 time faster than the SPICE model.=20

In particular, show me how your driver model can model the impact of SSO =
on
the feedback clamp and pass gate substrate and show me how your model =
can
distinguish the impact between when the predriver ground is tied to the
drivers ground return or if it is separated and tie to core ground. Can =
you
dig it ? Bare in mind that is a more than 10 year old circuit and it =
only
has less than 10 transistors. I haven't even suggest the latest and =
greatest
circuits I have come across recently.

Jon, go ask Chris how fast his full behavioral models ran given the
packaging and topology requirements. Is it 300 times faster or even 30 =
times
faster ? I don't think so. Your assumption that full transistor =
description
of a circuit takes orders of magnitude to simulate vs. a behavioral =
model
with the complexity to accurately represent it is simply not true.

I think there is this myth of SI work is simulating every net on the PCB =
in
order to sign off a post route PCB design and therefore unless you have =
a
simulator that can handle a net a minute, your task of SI check is =
doomed. I
happened to not believe in such practice and like to concentrate on =
using
accurate models to predict the bus performance pre-route and generate =
the
right routing rules so that the post route checking is a length, =
topology
and parallelism check rather than IBISing or SPICEing every net. Driver =
and
receiver tuning is the single most important task I do with all the I/O
designer I have, including Bill. I cannot afford to have the circuit
tweaking "lost in translation" between the transistor models and the
behavioral ones. Especially when things as subtle as SSO impact on
pre-driver or substrate or charge kick back in S/H receivers, I simply =
don't
have the time and bandwidth to waste on checking the correlation between =
the
IBIS model and SPICE. Its a fun science project I don't have time to =
enjoy.

But then again, I am just a dumb engineer.

-----Original Message-----
From: Jon Powell [mailto:jonpowell@xxxxxxxxxxxx]
Sent: Thursday, April 29, 2004 9:16 AM
To: arpad.muranyi@xxxxxxxxx; Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: [SI-LIST]: Which tool is the best - =
LINPARdisc
ussion


To agree and expand on Arpad's comment, another issue I believe in is =
the
idea of "accuracy matching". Unless you really enjoy sitting around and
waiting for your simulations to finish, it is a reasonable idea to want =
to
simulate as fast as you can for the best accuracy. I mean, if you can do =
two
simulations and one takes 1 minute and one takes 1 hour and they give =
the
same answer, which do you want? And accuracy is not determined by just =
the
driver model. In many cases it is determined much more by the level of
accuracy of all of the input data. How well do you really know your Er
(10%?) or even your actual trace width and spacing (another 10%?). How =
much
tolerance do you have in general across a fab run on your boards? What =
about
changes due to temperature? You add all these things up and you see that
there is an accuracy limit imposed by your lack of exact knowledge of =
what
you are simulating. This is especially bad in situations where the =
return
path is not obvious or perhaps widely distributed. So running a =
simulation
that is "more accurate" (or has more
precision) than your input data won't give a better answer, it will just
take longer.

jon


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx =
[mailto:si-list-bounce@xxxxxxxxxxxxx]On
Behalf Of Muranyi, Arpad
Sent: Thursday, April 29, 2004 1:02 AM
To: Chris Cheng; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: [SI-LIST]: Which tool is the best - LINPARdisc =
ussion


Chris,

I do not want to react to every single thought in your message, but I =
feel
(for the sake of the rest of the readers) that I should mention that the
situation is not as bad as you paint it.

It is true that in the past IBIS lagged behind the bleeding edge =
technology
because it took so long to come up with new keywords for the new =
behaviors
in the latest buffer types (such as GTL).  However, now that we have =
these
new language extensions, the IBIS specification will not have to be
"tailored" to every new buffer behavior that designers com up with.  It =
will
be only up to the model maker how long it will take to see a behavioral
model for a new buffer design.

Second, I can understand many of your reasons that you makes you want to
stick with transistor level models.  However, don't forget that these
behavioral models can run much faster than full transistor level models, =
I
measured close to 300x speed improvements on one of the PCI-express =
designs.
If you want to run thousands of signal integrity simulations with a =
model
that takes 30 minutes (or more) for each run you will never get your =
work
done...

Arpad
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D
=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D=
3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D=3D3D
=3D3D=3D3D=3D3D=3D3D=3D3D

-----Original Message-----
From: Chris Cheng [mailto:Chris.Cheng@xxxxxxxxxxxx]=3D20
Sent: Tuesday, April 27, 2004 11:53 AM
To: Muranyi, Arpad; si-list@xxxxxxxxxxxxx
Subject: RE: [SI-LIST] Re: [SI-LIST]: Which tool is the best - =
LINPARdisc
ussion


Sure, anything is possible. And the dog ate my homework.
Just kidding. Little bird always reminds me that those are very smart =
people
and he is always grateful for the work they have done. And I am told at
least one of them got it reasonably fast on first try. =3D20 I never got =
paid
to create industry standards or sell CAD tools.My current or former
employers just pay me to make sure their own or customers systems work. =
Very
smart circuit designers gave me very smart I/O. I am just lucky to even =
have
a circuit description of it. To ask me to generate an accurate =
behavioral
abstraction of it everytime something new comes out is beyond my limited
intelligence. Case and point is the original GTL driver by Bill Gunning =
with
the delay feedback for my first GTL system, I can't even remember how =
long
did it take (or if ever) for IBIS to be able to generate an accurate =
model
of it. And if at the end of the day those so call tools "will get better =
in
the future" or "be able to do what you want in the next rev" or "add x =
tool
to y tool and you may be able to do that", that's just too complicated =
for
me. Remember, I am just a dumb engineer who wants one tool to do it all.
Seems like I've been lucky so far with what I've got and I'll probably =
stick
with it for awhile.


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