[SI-LIST] [SI-LIST]: Pull-up resistor value

 Hi all,   I am facing trouble in fixing the pull-up resistor value for CMOS
devices. There are 2 scenarios where i have to use pull-up resistors. First
is that i wish to provide a steady high logic level during reset and hence i
use a pull-up resistor at the input of the intended IC. I am not able to
determine the appropriate value of the resistor. Second scenario is that
wheni tie two or more open-drain ouputs together to VCC to achieve wired
logic. In this case too i do not know as to how to arrive at the optimum
value of the pull-up resistor. I am able to arrive at the min and max value
of the pull-up resistor based on the following equations: 

1>  Rmax = (VCCmin - Vih min)/n*Ileakage and 

2>   Rmin = (VCCmax - Vil max)/ Iol max 

The min and max values thus obtained are far too much in the extreme ( eg,
100ohms and 300Kohms) that i am not able to arrive at the optimum value. Can
anybody out there throw some light on this based on his/her experience. Also
am i missing out on any other parameters when i choose the optimum value. 

Also can anybody out there tell me the circumstances under which one would
gofor a strong or a weak pull-up. 

  

Thanx in advance. 

Anand Kuriakose, 

Force Computers 

 

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