[SI-LIST] Re: [SI-LIST]: Distribution/Filtering/Decoupling Guide The 100Mhz clean cut off.

The scary comment wasn't about your proposal but it was about taking
data off of one design and applying it. You are trying to address this
problem by coming up with a method of finding out how power distribution
to and noise leaving uproc, FPGA, ASICs, different designs vary. I also
was not questioning other people's findings but I think that different
designs can have major differences. I have seen designs that break the
100Mhz cutoff (this problem can be exacerbated if you have VCO's or
resonances that are very sensitive to specific frequencies)

Any one who has been in the business any length of time has seen one of
the "rules" they came up with extended into places that no longer apply.
That was my concern here.

Mark said it well
"Based on that, we can intelligently evaluate our own=20
deviations from the standards". As long as this is done then we are
fine.=20

The process of coming up with a universal test platform is tough but it
is being done in 2nd level qual. issues and this will have a large
benefit but the amount of work to get there was fairly large. They had a
similar problem - all the chips could have vastly different
pinouts/sizes/etc.=20

Thanks
Ed=20


-----Original Message-----
From: Michael E. Vrbanac [mailto:vrbanacm@xxxxxxxxxx]=20
Sent: Friday, January 16, 2004 11:58 AM
To: Ed Priest
Cc: si-list@xxxxxxxxxxxxx
Subject: Re: [SI-LIST] Re: [SI-LIST]: Distribution/Filtering/Decoupling
Guide The 100Mhz clean cut off.

Ed,

Let's take the scariness out of it.  If that's not the way to do it,
then
let's all figure out a way to do it correctly.  As you said, there are a

lot of
variables out there.  The truth is a lot of people do this.  If you
think we
need to replace that (probably not a bad idea) whatever replaces it
needs
to be about as simple a decision to make or at least make the extra
effort
worth the time to do it.  So tell us how you'd do it or at least what
you think
are the pertinent issues to address.

Best Regards,

Michael

At 10:06 AM 1/16/2004 -0800, you wrote:
>This is getting scary. Please do not globally take the number of
>required power and grounds on a specific project and apply it to all
>applications. Microprocessors, FPGA's, ASSP, ASICs all have a different
>on chip environment. The amount of on chip capacitance, the closeness
of
>the di source to the chip capacitance, the presence of on chip mixed
>signal IP, all could make reducing the number of power and grounds a
bad
>idea. Increasing the inductance to the board has a good chance of
>increasing the coupling between different parts of the chips. Again,
>microprocessors where both the circuits and power distribution are
>custom designed can have a lot more friendly environment then other
>chips you deal with.=3D20
>
>This discussion and work can be very beneficial but applied incorrectly
>can have disastrous effects.
>
>Ed
>
>-----Original Message-----
>From: Ravinder.Ajmani@xxxxxxxx [mailto:Ravinder.Ajmani@xxxxxxxx]=3D20
>Sent: Friday, January 16, 2004 8:35 AM
>To: Chris.Cheng@xxxxxxxxxxxx
>Cc: silist
>Subject: [SI-LIST] Re: [SI-LIST]: Distribution/Filtering/Decoupling
>Guide The 100Mhz clean cut off.
>
>Chris,
>Thanks a lot for the excellent explanation.  Will you please tell me
>what=3D20
>is the adequate number of power and ground pins for a 324 pin BGA
>package.=3D20
>  We use this package in two versions, C4 attach and wire bonded.
>Regards, Ravinder
>Server PCB Development
>Hitachi Global Storage Technologies
>
>Email: Ravinder.Ajmani@xxxxxxxx
>
>
>
>
>Chris Cheng <Chris.Cheng@xxxxxxxxxxxx>
>Sent by: si-list-bounce@xxxxxxxxxxxxx
>01/15/2004 06:56 PM
>Please respond to Chris.Cheng
>
>=3D20
>         To:     "'Charles Grasso'" <cgrassosprint1@xxxxxxxxxxxxx>,
Chris
>Cheng=3D20
><Chris.Cheng@xxxxxxxxxxxx>, "'Larry Smith'" <Larry.Smith@xxxxxxx>
>         cc:     scott@xxxxxxxxxxxxx, silist <si-list@xxxxxxxxxxxxx>
>         From:   si-list-bounce@xxxxxxxxxxxxx
>         Subject:        [SI-LIST] Re:
Distribution/Filtering/Decoupling
>Guide The 100Mhz clean=3D20
>cutt     off.
>
>
>
>
>Well, I will give it a try based on what I now see as a complete
picture
>
>of
>what's going on with Larry's example.
>
>Disclaimer first
>Since I was responsible for a lot of packaging and module designs =
in=3D20
>Larry's
>company before I departed many years ago, I have to say I have never
>seen=3D20
>or
>reviewed or involved in any of the current or whatever future
generation
>package or module he is referring to. Everything I am saying is
simply=3D20
>based
>on what Larry has disclosed in this public forum. If my guess is wrong,
>please accept my apology.
>
>To begin the discussion, I have to requote Zhiping's question below on
>how
>to "shift the power integrity problem to the PCB level". I claim there
>is=3D20
>a
>hard limit of 100MHz on the package power distribution, by that I
mean=3D20
>with
>the existing number of pins/sockets and package caps and on die=3D20
>decoupling,
>all the available decoupling charge on the package and die will be=3D20
>consumed
>and core voltage will start to drop after 10ns of continues current
>drain=3D20
>on
>die. Something on the PCB and external DC/DC regulator has to start
>providing the charge to maintain the voltage level on die. By the same
>token, due to the exiting impedance at the pins/socket and package, the
>system (PCB or regulator) cannot reach the Si core power faster =
than=3D20
>100MHz.
>This is based on an optimized pin analysis where I want to provide
the=3D20
>least
>amount of power and ground pins (if you ship a huge volume, like a 100M
>of
>them, @ a few cents per pin, you save a LOT of money) that can
maintain=3D20
>the
>minimum core noise level on die. The added benefit of it is you don't
>need
>to demand exotic >100MHz decoupling outside the package (since it
won't=3D20
>help
>anyways) and you also don't need to over kill your decoupling on
package
>
>by
>providing <100MHz decoupling bulk caps, just pass that responsibility
to
>
>the
>system folks.
>
>Now let's say you throw in too many power and ground pins on your
>package.
>Not only does it cost you money (@ a few cents per pin), it now =
also=3D20
>starts
>to perforated your PCB power and gnd planes to the extend that the PCB
>to
>package impedance starts to pick up (shifting below 100MHz). Now =
you=3D20
>really
>need to have a thin core PCB to lower the impedance back to equal the
>case
>when you have less power/ground pins with a smaller package. But in
a=3D20
>sense,
>this is exactly what Zhiping was asking for, shifting some of the=3D20
>integrity
>problem to the PCB level. You can over design to an extend that =
what=3D20
>happen
>in the PCB really start to impact the package performance.=3D20
>
>It's your choice, too many pins and you will need BC and cost you
>$$$$$$,
>just enough pins and you don't need BC and save you some $ also. But
if=3D20
>you
>don't have enough pins, you are dead and no system or PCB design can
>save
>you.
>
>As a side note for those who want to built benchmark system design to
>evaluate system to package distribution, good luck ! If you think you
>can
>pick up something as subtle as the above, my hats off to you. I =
have=3D20
>enough
>trouble doing a unique case where I know everything ahead of time.
>
>Same old song here, there is no need for BC. Hey, that may be in my
>second
>broken record.
>
>-----Original Message-----
>From: Charles Grasso [mailto:cgrassosprint1@xxxxxxxxxxxxx]
>Sent: Thursday, January 15, 2004 5:34 PM
>To: Chris.Cheng@xxxxxxxxxxxx; 'Larry Smith'
>Cc: scott@xxxxxxxxxxxxx; silist
>Subject: Distribution/Filtering/Decoupling Guide The 100Mhz clean cutt
>off.
>
>
>Chris, Larry et al...
>
>Can you please explain the 100MHz clean cut so often mentioned in ths
>thread? Is it bandwidth (i.e related to rise time?) is it the
crystal=3D20
>or...
>
>Puzzled.
>Chas in Colorado..
>
>
>-----Original Message-----
>From: zhiping yang [mailto:zhiping@xxxxxxxxx]
>Sent: Tuesday, January 13, 2004 5:55 PM
>To: Chris.Cheng@xxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>Subject: Re: [SI-LIST] Re: Power Supply
>Distribution/Filtering/Decoupling Guide]
>
>
>Hi Chris,
>
>Thank you for sharing your thoughts and Very good points about the
power
>integrity.
>
>One comment about your "total system approach".  Technically speaking,
>it=3D20
>is
>best to put the equal amount of efforts on the die, package and PCB
>power
>distribution since they are equally important in the complete =
power=3D20
>delivery
>system.  More important, the PCB COULD NOT fix the problems with the
die
>
>and
>package power delivery systems in some cases.
>
>In the real word, when cost and $$ is involved, the trade-offes must be
>made, so the design may not be optimized in technical side.  For
>example,
>due to the high cost of die size increase and package limitations, it
>may=3D20
>be
>more cost effective by shifting the power integrity problem to the
PCB=3D20
>level
>at a certain degree.  This may require using BC or more decoupling caps
>on
>the board, but it could still be cost effective from the "total system"
>point view.
>
>This is my $0.02 input.  Thanks.
>
>Zhiping
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