[SI-LIST] SI Question 2 of 3: Differential clock lines over split in ground plane

I am working on a telecoms design with Analog and Digital areas.  The =
whole unit is=20
inside a thick metal box, with the PCB bolted and grounded to the =
chassis across the=20
board.  Various parts of the PCB are also further isolated by slots in =
the ground=20
and power planes and also by walls bolted to exposed ground plane on the =
top and=20
bottom of the board.

Here is an ASCII picture of small part of the board showing a digital =
area, analog=20
area, the slots isolating those areas and the soild metal wall. You will =
only be=20
able to see this picture properly in monospaced font

There are also two differential LVPECL clock traces providing a 75MHz =
clock to an=20
ADC in the Analog section. This pair crosses the slot about halfway =
along its length.=20
The ADC sits on the junction of the Digital and Analog ground planes. =20

What are the risks of the differential traces crossing the slot?  =
Particularly with=20
respect to degradation of noise margin in the analog zone.

|                             #########                   D I G I T A L  =
 G R O U N D
|                             #########
|                  +---------+#########                   =
+--------------------------
|                  |         |#########                   |              =
           =20
|                  |         |#########                   |              =
           =20
|                  |         |#########                   |         S L =
O T         =20
|                  |         |###   ###                   |              =
           =20
|                  |    S    |### W ###                   |              =
           =20
|                  |         |###   ###                   =
+--------------------------
|                  |    L    |### A ###                   =20
|                  |         |###   ###
|                  |    O    |### L ###
|                  |         |###   ###
|                  |    T    |### L ###                   A N A L O G   =
G R O U N D
|                  |         |###   ###
|                  |         |#########
|                  |         |#########
|     ------------------------#########--------------------- Diff+
|                  |         |#########
|     ------------------------#########--------------------- Diff-
|                  |         |#########
|                  |         |#########
|                  |         |#########
|                  |         |#########
|                  |         |#########
|                  +---------+#########
|                             #########
|                             #########
|                             #########
+------------------------------------------------------------------------=
------------

--
JP Coetzee  (was JP Nicholls) /  jpcoetzee@xxxxxxxx =
<mailto:jpcoetzee@xxxxxxxx>=20
=20
Digital Design Engineer
=20
Powerwave UK Ltd
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