[SI-LIST] SI Modeling Tutorial/Survey at PCI SIG DevCon-Europe and DesignCon 2006

Please be advised of three upcoming opportunities to learn more about
the details and applications of the new AMS modeling standard.  These
100% technical sessions will be of interest to model suppliers, model
users, and SI tool vendors.  These are a great way to become familiar
with the exciting capabilities of this new industry standard. =20


PCI SIG DevCon-Europe
Wednesday, January 25, 11:30 AM
Queen Elizabeth II Convention Centre
London, England
http://www.pcisig.com/events/devconeurope06
Electrical Modeling Alternatives and Languages

Choosing a Signal Integrity verification technique can be confusing with
all the simulation and modeling choices available today.  This
presentation will go through the most common choices available, and
describe the primary strengths and weaknesses of each.  The presentation
will go on to detail the features of the new IBIS 4.1 AMS SI modeling
standard, and demonstrate how it can be used in simulations that are as
accurate as transistor-level SPICE but hundreds of times faster.  The
presentation will show a case study of modeling a PCI Express driver in
AMS, and will conclude with examples of other novel applications of IBIS
4.1 and AMS (such as automated measurements, CDR, and DFE). =20


DesignCon 2006
Monday, February 6,  9:00 am - noon
Santa Clara Convention Center
http://www.designcon.com/2006/
TF-MA2: Introduction to IBIS 4.1 AMS SERDES Driver Modeling, and Other
Novel Applications of AMS Modeling=20

Modeling SERDES drivers has proven to be a significant challenge with
traditional modeling techniques. Fortunately, the IBIS committee
recognized this problem and ratified a new approach which offers
significant advantages over existing techniques. This tutorial will
enable the participant to understand and perhaps begin coding their own
IBIS 4.1 models. This skill will be exercised by going through a number
of actual examples of the standard and novel applications of its new
capabilities (such as DFE). This presentation will show how IBIS 4.1/AMS
is like having your own simulator programmer on staff.  The applications
are only limited by the imagination.=20


User2User 2006
Thursday, May 4, 2006
San Jose Marriott and Convention Center
www.mentor.com/u2u
Functional SI Simulation using IBIS 4.1 and HDL models

Just at the time it is becoming critical to perform a thorough SI
analysis on a dynamic memory interface design, it is becoming
increasingly difficult to perform such an analysis. High signal
edge-rates, advanced techniques such as dynamic termination, complex
requirements such as slew-derated timing, and critical pattern-dependant
crosstalk issues are presenting significant challenges to today's
designer of DDR2 and DDR3 memory interfaces.  This joint paper with
Micron will demonstrate an analysis technique using the latest SI
standards that provides a thorough automated analysis of a complete CPU
to DDR interface in one simulation.


fyi: Given a sufficient audience the first presentation can be
customized to specific company needs and delivered on-site or via WebEx.
Please also be advised that free modeling services are available to key
silicon vendors getting started in offering their customers the
capabilities of these models.  Please contact me for details.


I hope to have the opportunity to meet you at one of these events.


Regards,

Gary Pratt




Gary L. Pratt, P.E.
Product Manager - High-Speed Design Kits SDD Division
Office: (503) 685-1177
Mobile: dial '0' at Voicemail, or
mobile: (262) 337-2196
Email: gary_pratt@xxxxxxxxxx


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