[SI-LIST] SI Clarifications
- From: suresh <sureshkumar.v@xxxxxxxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Tue, 11 May 2004 17:07:28 +0530
Hello SI Expert Team ::
Pls clarify the following signal integrity issues.
1) We design WLAN cards with PCI as the host interface.Threre is a 33 Mhz
clock which comes from the CPU to the pci edge connector of our card as a
part of pci standard.I have seen on quite a few ethernet cards( NIC cards)
in which this 33 mhz clock signal from CPU comes to the ethernet cards
edge connector is taken to the internal ciruitry through a curved path
(with some 5 to 6 curves) and not as a straight line.Pls clarify as how
this helps the signal integrity.
2)For ADC (Analog to Digital Converter) we do use separate analog and
digital ground planes.The basic ground comes to our ADC(second) card from
other Digita FPGA l(First) card.Pls specify the ground comming from the
first FPGA card to the ADC card should be taken as the analog ground plane
or the digital ground plane.
Best Regards
--
suresh
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