[SI-LIST] Re: SERDES CDR with asynchronous reference clock?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
- Date: Thu, 10 Dec 2009 10:23:21 -0800
Ivor, yes that is pretty much it. When the channel detects data loss,
the VCO locks to the local clock in order to reduce lock time when data
reappears. As long as each transmitter operates within the absolute
clock tolerance the channel works. Ethernet has worked this way for a
long time. The disadvantage of distributing clocks through trees is
jitter accumulation.
Steve.
Bowden, Ivor wrote:
> Thank you Steve! Please let me reiterate to make sure I understand you.
>
> "The Rx clock controls data transfer AFTER buffered CDR" is the key thing I
> was missing, the CDR will always have a PLL or some other type of clock
> regeneration recovered from the RX data stream.
>
> In addition, to quote an off list reply I received (thanks Leonard) "When
> there is no data or no lock the internal PLL will normally frequency/ phase
> lock onto the reference clock".
>
> Is this summary of the three PCIE RX clock architectures correct:
>
> Common Clock
> The host transmits a common reference clock (RefClk) that is used by the
> downstream device e.g. ExpressModule for both TX and RX. The downstream
> device has a PLL that is frequency locked to the RefClk and phase locked to
> the RX data.
>
> Data Clock
> It is not necessary to have a common reference clock. The downstream device
> has a PLL that is frequency and phased phase locked to the RX data. This
> clock could also be used by the downstream device for TX, or it could use a
> separate TX clock within 600ppm of the RX clock.
>
> Separate Clock
> It is not necessary to have a common reference clock. The downstream device
> has a PLL that is frequency and phased phase locked to the RX data. This
> clock could also be used by the downstream device for TX, or it could have a
> separate TX clock within 600ppm of the RX clock. In the absence of data, the
> RX clock is locked to the local reference clock.
>
> ?
>
> Noted that (per Leonard) "There are many other ways to perform asynchronous
> sampling in the digital domain", so the each above summary method would just
> be one (typical?) way.
>
> Comments welcome.
>
> Thanks,
>
> Ivor
>
> -----Original Message-----
> From: steve weir [mailto:weirsi@xxxxxxxxxx]
> Sent: Thursday, December 10, 2009 12:43 AM
> To: Bowden, Ivor
> Cc: si-list@xxxxxxxxxxxxx
> Subject: Re: [SI-LIST] SERDES CDR with asynchronous reference clock?
>
> Ivor, the receive CDR phase locks onto the incoming data stream and dumps the
> data into an elastic store: FIFO. The Rx clock controls data transfer after
> buffered CDR. Channel utilization is under 100% by more than 2X the clock
> tolerance. Therefore a transmit stream will never exceed the receiving end's
> ability to absorb the data.
>
> Steve.
> Bowden, Ivor wrote:
>
>> Hi SI people,
>>
>>
>> Can someone offer an explanation how a SERDES CDR can recover data with an
>> asynchronous reference clock? Example is PCI-Express (reference PCI EXPRESS
>> BASE SPECIFICATION, REV 2.1 section 4.3.7.5. "Separate Refclk
>> Architecture"), where Refclk #1 drives the TX circuit and Refclk #2 drives
>> the RX circuit. How does this CDR circuit work? I thought that even if they
>> were separate clocks they'd have to be frequency locked, and a PCI-SIG
>> presentation indicates they can be +/-300ppm each.
>>
>>
>>
>> Thanks,
>>
>>
>>
>> Ivor Bowden
>>
>>
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