[SI-LIST] Re: SERDES CDR with asynchronous reference clock?
- From: steve weir <weirsi@xxxxxxxxxx>
- To: "Bowden, Ivor" <ibowden@xxxxxxxxxxxxxxxxx>
- Date: Thu, 10 Dec 2009 00:42:44 -0800
Ivor, the receive CDR phase locks onto the incoming data stream and
dumps the data into an elastic store: FIFO. The Rx clock controls data
transfer after buffered CDR. Channel utilization is under 100% by more
than 2X the clock tolerance. Therefore a transmit stream will never
exceed the receiving end's ability to absorb the data.
Steve.
Bowden, Ivor wrote:
> Hi SI people,
>
>
> Can someone offer an explanation how a SERDES CDR can recover data with an
> asynchronous reference clock? Example is PCI-Express (reference PCI EXPRESS
> BASE SPECIFICATION, REV 2.1 section 4.3.7.5. "Separate Refclk Architecture"),
> where Refclk #1 drives the TX circuit and Refclk #2 drives the RX circuit.
> How does this CDR circuit work? I thought that even if they were separate
> clocks they'd have to be frequency locked, and a PCI-SIG presentation
> indicates they can be +/-300ppm each.
>
>
>
> Thanks,
>
>
>
> Ivor Bowden
>
>
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