[SI-LIST] Re: Rocket I/O models for hspice

Hi Srivatsan
I suggest you to start with the examples given with the models.
There are also plain explanations of how to use them.
As you try the examples and customize one for your application, you will
be able to understand why it doesn't work.
I send you some pdf of the model (I think you are using the V4), you can
also find them in the siskit.
What is the reported error in Hspice?
Best regards,
        Giovanni 
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Srivats Partha
Sent: 25 June 2006 04:32
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Rocket I/O models for hspice

Hello Gurus
I need to simulate the rocket I/O transmiter and receiver in hspice. I
downloaded the models from the Xilinx website. It says those models are
encrypted and are executable directly in hspice but somehow i cant get
those models working in hspice. Has anyone used the rocket I/O models
for  hspice , If so please help me out?  Thanks in advance
regards
srivatsan


--
I have no special talents. I am only passionately curious. AE
 __________________________________________________
Do You Yahoo!?
Tired of spam?  Yahoo! Mail has the best spam protection around 
http://mail.yahoo.com 

------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl?Si-List_FAQ

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu
  



-- Attached file included as plaintext by Ecartis --
-- File: virtex4-rocketio_sis_kit_readme.txt
-- Desc: virtex4-rocketio_sis_kit_readme.txt

===================================================================

XILINX VIRTEX-4 ROCKETIO SIGNAL INTEGRITY SIMULATION KIT

RELEASE 2.0

RELEASED ON DECEMBER 12, 2005

COPYRIGHT  2005   XILINX, INC.

ALL RIGHTS RESERVED

ANY UNAUTHORIZED COPYING OR EDITING OF THIS DOCUMENT OR ANY OTHER 
CONTENT OF THIS KIT IS CONSIDERED ILLEGAL AND WILL BE PROSECUTED 
TO THE FULL EXTENT OF LAW.

===================================================================

DISCLAIMER FOR THE CURRENT RELEASE

1. The models provided in this release have not been fully
correlated with actual fabricated devices. These models are based on 
the design simulations, and is dependent upon the device models 
received directly from the fabrication foundry. The models in this
kit are subject to change in the future based on characterization results.
Users are strongly recommended to periodically check with Xilinx for any 
update to this kit.

2. HSPICE users

This kit has so far been simulated with the Synopsys HSPICE UNIX 
Version 2003.3.  Use of any earlier version of HSPICE or 
any other spice simulator is not recommended for this kit. There may be minor 
differences between the results from the UNIX and PC versions of HSPICE
due to any inherent simulator differences.
simulator.

3. Eldo users (Eldo support added at a later date)

This kit has so far been simulated with the Mentor Graphics Eldo (PC) 
Version v6.5_2.1.  Use of any earlier version of ELDO or any other spice 
simulator is not recommended.

References to HSPICE below can generally be replaced by 'Eldo'.  For example, 
when referring to a directory '/HSPICE/Subckts', Eldo users should look for
the corresponding '/Eldo/Subckts' directory. 

INTRODUCTION

This signal integrity simulation kit enables a user of the Virtex-4
FPGA to simulate any system configuration that will comprise a RocketIO
transceiver. This kit includes the models of the line driver of the 
transmitter (TX) and the analog front end of receiver (RX).  This kit 
provides the user with a way of creating input patterns with any specified 
amount of jitter. The specific input patterns that are provided ready-made 
with this kit do not add jitter.  As a result, additional margin at the RX
eye diagram is required to accommodate the TX jitter.

In addition to the TX and RX models, the MGT clock models are included. These
are device-level models to allow users to verify that their clock inputs have
adequate swing and common mode levels to drive the MGT clocks.

ADDITIONAL DOCUMENTATION

Various settings that are needed for proper operation of these models 
are described in the "Virtex-4 RocketIO Multi-Gigabit Transceiver User Guide" 
(ug076, v1.3 or later).

INITIAL RELEASE LIMITATIONS

The V4 Receiver (RX) has an active linear equalizer providing both adjustable
DC and frequency-dependent gain.  This active linear equalizer is then
followed by a decision feedback equalizer (DFE).  Although the intent is for
either linear or DFE (or both) to be used for best performance, for this 
release only the linear equalizer is supported.  

ENCRYPTION

To preserve the intellectual properties of both the fabrication foundries
and Xilinx, the device (transistor, resistor, capacitor) models and 
RocketIO models are encrypted. Users should be able to use these encrypted
models seamlessly.  Attempts to decrypt these encrypted models will be 
considered a violation of law. The S-parameter models of channel and package 
are not encrypted; they are, however, protected under the Xilinx license 
agreement; these S-parameter models can only be used to simulate with Xilinx 
RocketIO TX,RX, and MGT clocks.

ORGANIZATION OF THE KIT

The kit has several directories which host relevant models. Also certain 
system solutions using the RocketIO TX and RX are provided as examples.
The following text describes contents of each directory as well as comments
on use of the contents.

DOCUMENTS (in /Docs directory)

The /Docs directory contains this readme file and any other relevant 
documentation.  ASCII files may have formatting/character problems while 
being transferred from UNIX to PC or vice versa. "dos2unix" or "unix2dos" 
commands should be run on these files to view and operate these files properly. 
Most notably, an ASCII file, if transferred from PC to UNIX, may add
superfluous ctrl-M (^M) characters at the ends of lines. These ^M
characters can be removed with the dos2unix command.

There are three figures describing example netlists in the /HSPICE/Examples.  
These figures show subcircuits, nodes, control parameters, power supplies, and 
other details.  The MGTCLK netlist is documented with the ug244_01.pdf figure.
The TX and RX in the V4TXRX netlist is documented with ug244_02.pdf and 
ug244_03.pdf, respectively.

CIRCUIT MODELS (in /HSPICE/Subckts directory)

The Subckts directory contains:               
V4_TX.sub: TX model
V4_RXAFE.sub: RX model with linear equalizer (AFE)
MGTCLK.sub: MGT clock model
misc_params.inc: parameters needed by device library
d2a.sub: used with TX and RX models to control settings with '1' or '0'
fir3_source.sub:  converts single pwl source to 3-tap differential source
                    needed by TX

DEVICE MODELS (in /HSPICE/Libary directory)

The  Library directory contains library files which needs to be included 
in any simulation setup in HSPICE.  All these model files are encrypted. 

CHANNEL MODELS (in /Channel_Models directory)

Ten channel models are provided as 4-port S-parameters in Touchstone
format. There are five models meant to approximate line lengths of 10, 15,
20, 30, and 40 inches.  The lines are modeled as 50 ohm, 6mil wide copper 
striplines with dielectric loss tangents of 0.02. These models are repeated 
but with two connector models inserted in to the channel to emulate a 
backplane connected on either side to TX and RX daughter cards.  The connector
models are inserted within 2 inches of either side, i.e., the daughtercard
stripline lengths are 2 inches and the backplane lengths are 4 inches shorter
than the total lengths.  The file names are self-descriptive by indicating
line lengths and whether connector models were inserted.  The connectors are
modeled with 400ff daughtercard and 800ff backplane capacitances separated
by with 4mm of low-loss 50ohm transmission line.  This simple connector 
model is intended to approximate a HMZD connector with no pcb via stubs and 
large anti-pads around these pcb vias. These models have frequency points 
starting at 1 Hz increasing on a log scale to 50 Ghz.


INPUT PATTERNS (in /Stimulus directory)

Example input patterns and the means to create them are found in the Stimulus
directory.  In this directory is a perl script, 'spice_vsource_gen.pl' which
you can use to create your own pwl source. The perl script requires an input 
bit pattern such as the example 'bp_prbs_2^7-1.txt' which is a 2^7-1 PRBS 
127 bit long pattern.  The top section of the perl script well documents 
the many parameters accepted by the script.  To help manage the parameters, a
file called 'vsource_params.txt' is created to record the command line to use
as a reference for setting the parameters.  

The example netlists were set up with those parameters as listed in the 
'vsource_params.txt' file, specifically for the 5 Gbps example as set
by the '-r5e9' flag. Note that all parameters are of the form '-?' where
the dash is required followed by one single character (case is important).
Other parameters of note are the -b10000 flag which sets up a source 
with 10,000 bits.  The PWL source HIGH and LOW states are set up with 
the '-h1.0' for a 1.0Volt HIGH level and '-l0' for a 0Volt LOW level. 
The pwl source begins with average values of HIGH and LOW states, which
is 0.5Volts in this example, then after one bit period it replicates the
bit pattern found in the file 'bp_prbs_2^7-1.txt', which is the last field.
If the number of bits exceeds the bit pattern length, then the pattern is 
repeated until the requested number of bit is reached.  It is important to 
keep the number of bits greater than what will be simulated (as dictated by the 
.tran statement) otherwise the pwl source will stay at the last defined 
voltage.  Also, using the 'R' parameter in the .tran HSPICE command will not 
work to repeat a PWL source since this source begins at the average of the 
HIGH and LOW values.

An offset voltage can be selected but in this case was set to zero with
the '-o0' parameter.  The pwl source is applied across nodes 'in' and 'ref'
with the '-vin,ref' parameter.  No jitter is applied as set with the
'-j0e-12' parameter.  This jitter is pk-pk.  For example, 30psec of pk-pk
jitter could have been added by instead using a 'j30e-12' parameter setting.
The jitter is hard-coded as a simple 100Mhz modulation to quickly simulate
eye closure due to jitter.  For optimum speed, set the jitter to zero
and allow more margin for jitter at the RX in the simulations.

Using the '-s' flag wraps a sub-circuit called 'vpwl' around PWL source so 
that its node names can be changed when the vpwl sub-circuit is instanced. 
The edge rate of the pwl source is set with 't.2' parameter which means that
the edge rate will be 0.2 times the bit_period.
 

EXAMPLES (in HSPICE/Examples directory)


Please read ug076 to gain an overview of the functions of TX and RX settings.

The main example is the V4TXRX.sp netlist.  It starts with a 1.25Gbps example
of an RX driving a TX over a 40 inch backplane model (with connectors). For
the low data rates, both pre and post TX equalization taps are powered down.
The TX output is set to 1/2 swing and the slew rate is set to its lower of
two settings.  The RX emphasis is maximized.  The RXE analog front-end (AFE),
which is also known as the 'linear receiver' provides little emphasis at
this lower data rate.  But little is needed since AC losses are low.  If
any equalization is needed, then it is best to maximize the RX (but don't
over equalize) then use TX equalization if needed.  The RX gain was also 
maximized since it is generally more power-efficient than adjusting the TX
for more gain since the TX must drive a 50 ohm system.

The V4TXRX.sp netlist is well-documented and you can customize the netlist
to your application while trying to change various settings to optimum
performance.  The netlist has several alter statements where examples are
shown for 2.5, 3.125, 5, and 6.25 Gbps.  As frequencies increase the channel
lengths go down.  The TX is set to full swing (was 1/2 swing for 1.25Gbps). 
For these cases, the RX equalization and gain settings were left at their 
maximum levels.  The TX post emphasis was enabled and a little TX emphasis was
employed.  Good results were obtained for all these higher data rates
since the RX equalization profile matched well to the channel losses at the
differing data rates.   At a fixed data rate, the TX equalization can be
fine-tuned to maximize performance.  Or if performance is more than adequate,
then the TX data and post taps can be dropped proportionally to reduce 
swing and save power.  For some channels, it may be useful to turn on a little
pre tap emphasis-particularly for high data rates.


The last two .alter cases provide an example of how to model slow and fast 
corner cases.  The data rate is 6.25Gbps.  The fast case is using FAST process, 
TEMP=-40, and voltages 10% higher than nominal.  The slow case uses SLOW
process, TEMP=100, and voltages 10% lower than nominal.   Note that these
temperature extremes are for an industrial rating whereas the commercial
rating is 0 to 85. 

There is another TX/RX example, called "V4TXRXdual.sp" which shows how to 
use multiple TX and/or RX.  Essentially, it is a standard procedure where
the TX or RX subckt call is invoked again and the nodes are renamed to keep
them unique.  Since all the settings are controlled by the d2a sub-circuit
calls, then these d2a circuits need to be replicated and set to drive the
added TX or RX.  In the example provided, each TX and RX received the same 
power so those nodes were not repeated.  Similarly, one need only reproduce
all d2a sub-circuits for those settings which are unique.  For example, if 
two channels were to be simulated with slightly differing channel lengths,
then just share most of same settings between both TX and RX.  It is
likely that the optimal setting each channel differs from one another by 
a small change in TX equalization so only those TX equalization settings
need to be unique.  

It is not very efficient to model multiple TX and/or RX within the same netlist.
However, there may be cases of concern, such as connector crosstalk, where
modeling multiple TX and RX is the best method to validate conformance. 

Use the MGTCLK.sp netlist to verify that you've applied the correct swing for
AC coupled application.  Or that you've supplied the correct common mode
and swing for DC coupled applications.  It is recommended that AC coupling
be used to ensure the the MGTCLK input self-biases to its optimum level.


PACKAGE MODELS (in /Pkg_Models directory)

This directory contains two package models which are S-parameter files.
The first model is a TX or RX signal pair and the second is a MGT clock pair.
These models are not actual extractions of any of the V4 FX packages, but
represents the general FX packaging and is adequate for the purposes
of simulating full channels.  
 
Package models have ports 1/2 at the respective P/N solderballs (pin-side)
and ports 3/4 at the respective P/N chipbumps (die-side).

The example TXRX HSPICE example netlists do not incorporate the package models
due to convergence problems encountered by chaining s-parameters together. 
If convergence problems arise from using multiple s-parameter models, then
it is recommended to combine all the s-parameters into one touchstone file.
Using one s-parameter file also speeds up simulation time.

-- Binary/unsupported file stripped by Ecartis --
-- Type: application/octet-stream
-- File: ug244_01.pdf
-- Desc: ug244_01.pdf


-- Binary/unsupported file stripped by Ecartis --
-- Type: application/octet-stream
-- File: ug244_02.pdf
-- Desc: ug244_02.pdf


-- Binary/unsupported file stripped by Ecartis --
-- Type: application/octet-stream
-- File: ug244_03.pdf
-- Desc: ug244_03.pdf


------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field

or to administer your membership from a web page, go to:
http://www.freelists.org/webpage/si-list

For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field

List FAQ wiki page is located at:
                http://si-list.org/wiki/wiki.pl?Si-List_FAQ

List technical documents are available at:
                http://www.si-list.org

List archives are viewable at:     
                http://www.freelists.org/archives/si-list
or at our remote archives:
                http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
                http://www.qsl.net/wb6tpu

Other related posts: