[SI-LIST] Re: Right Angle Bends
- From: Jack Olson <pcbjack@xxxxxxxxx>
- To: Scott McMorrow <scott@xxxxxxxxxxxxx>
- Date: Wed, 20 Jul 2011 09:54:58 -0500
I just realized that was a really dumb question.
Can I retract that?
How can you route without bends?
I'm an idiot...
sorry.
On Wed, Jul 20, 2011 at 9:52 AM, Jack Olson <pcbjack@xxxxxxxxx> wrote:
> Thanks very much, Scott
>
> You have tools and knowledge that I never encounter here at my job (our
> designs have different constraints than many "SI-Listers", so I shouldn't
> have spewed my "real world" comment. Sorry)
> but...
>
> I would like to save this discussion for future reference, and since we are
> closer to nailing this down, could you make one further comment about 45
> degree bends if anything needs to be said about that? I don't think I've
> ever truly used a 90 degree bend in trace routing yet (24 years) although I
> can see 90 degree features in almost every design (like vias and exiting
> from rectangular pads, for example), but even our serpentine tuning uses
> round apertures and rounded bends (Mentor).
>
> That's why I had the assumption that talking about square apertures and 90
> bends (in trace routing) was only a mathematical exercise
>
> Since it is difficult for our CAD system to make "the optimal RF miter", we
> would probably use two 45 degree bends. Does anything need to be said
> about using round apertures with 45 degree bends? That's what I've seen in
> most board trace routing, except for the older tape-up designs.
>
> Thanks again for sharing your work,
> Jack
>
>
> .
>
> On Wed, Jul 20, 2011 at 7:58 AM, Scott McMorrow <scott@xxxxxxxxxxxxx>wrote:
>
>> **
>> Jack
>>
>> I've decided to put some numbers to the Right Angle Bend discussion, since
>> it's nice to know when we need to be concerned about a particular physical
>> phenomena.
>>
>> Your point regarding round apertures on traces is important, although
>> slightly misleading. A round aperture is applied to the end of a trace with
>> the center of the radius at the center of the trace width, such that the
>> outside apex is rounded, while the inside apex is square. Thus, a trace
>> corner with circular end apertures still has excess capacitance when
>> compared to the optimal RF miter[1]. If we use Bogatin's approximation of a
>> 50% miter (corner sliced diagonally in the center at 45 degrees, which is
>> not quite correct, but is close) to compute the excess capacitance, then
>> using a circular end aperture on traces at corners reduces capacitance by
>> (1-pi/4), or about 21%, which helps, but still leaves us with excess
>> capacitance.
>>
>> Here are some calculations based on Bogatin, "Signal Integrity
>> Simplified", page 317, which I've verified:
>>
>> Square corner capacitance(pf) = 40/Z0 x sqrt(Er) x w
>> where w = width in inches
>> Er = dielectric contstant
>> Z0 = characteristic impedance of trace
>>
>> 50 ohm impedance, Er = 4
>>
>> 10 Gbps (5 GHz Nyquist) with square apertures.
>> Case 1) A 100 mil wide trace - 160 fF = 199 ohm shunt Z at 10 GHz,
>> produces a 40 ohm tdr blip for 17 ps (17% UI).
>> Case 2) A 10 mil wide trace - 16 fF = 1990 ohm shunt Z at 10 GHz, produces
>> a 48.8 ohm tdr blip for 1.7 ps (1.7% UI).
>> Case 3) A 5 mil wide trace - 8 fF = 3980 ohm shunt Z at 10 GHz, produces a
>> 49.4 ohm tdr blip for 850 fs (0.85% UI).
>> Case 4) A 1 mil wide trace - 1.6 fF = 19900 ohm shunt Z at 10 GHz,
>> produces a 49.75 ohm tdr blip for 170 fs (0.2% UI).
>>
>> 20 Gbps (10 GHz Nyquist) with square apertures.
>> Case 1) A 100 mil wide trace - 160 fF = 99 ohm shunt Z at 10 GHz,
>> produces a 33 ohm tdr blip for 17 ps (34% UI).
>> Case 2) A 10 mil wide trace - 16 fF = 995 ohm shunt Z at 10 GHz, produces
>> a 47.6 ohm tdr blip for 1.7 ps. (3.6% UI).
>> Case 3) A 5 mil wide trace - 8 fF = 1990 ohm shunt Z at 10 GHz, produces a
>> 48.8 ohm tdr blip for 850 fs (1.7% UI).
>> Case 4) A 1 mil wide trace - 1.6 fF = 9947 ohm shunt Z at 10 GHz, produces
>> a 49.75 ohm tdr blip for 170 fs (0.3% UI).
>>
>> 20 Gbps (10 GHz Nyquist) With circular end apertures on traces (reduce
>> excess shunt capacitance by 21%)
>> Case 1) A 100 mil wide trace - 126 fF = 126 ohm shunt Z at 10 GHz,
>> produces a 36 ohm tdr blip for 17 ps (34% UI).
>> Case 2) A 10 mil wide trace - 12.6 fF = 1265 ohm shunt Z at 10 GHz,
>> produces a 48 ohm tdr blip for 1.7 ps (3.4% UI).
>> Case 3) A 5 mil wide trace - 6.3 fF = 2530 ohm shunt Z at 10 GHz, produces
>> a 49 ohm tdr blip for 850 fs (1.7% UI).
>> Case 4) A 1 mil wide trace - 1.26 fF = 12650 ohm shunt Z at 10 GHz,
>> produces a 49.8 ohm tdr blip for 170 fs (0.3% UI).
>>
>>
>> So, for real traces, on real boards, with real CAD end apertures, a single
>> corner on traces that are 1 mil to 10 mil wide, at frequencies of 10 GHz or
>> below, neffectively cannot be measured without specialized de-embedding
>> methods. The discontinuity is too small and too short. For microwave width
>> traces, those corners are large discontinuities with real consequences.
>>
>> If we happen to be running at 56 Gbps (28 GHz Nyquist)
>> Case 2) A 10 mil wide trace - 12.6 fF = 452 ohm shunt Z at 10 GHz,
>> produces a 45 ohm tdr blip for 1.7 ps (9.5% UI).
>> Case 3) A 5 mil wide trace - 6.3 fF = 604 ohm shunt Z at 10 GHz, produces
>> a 46 ohm tdr blip for 850 fs (4.8% UI).
>> Case 4) A 1 mil wide trace - 1.26 fF = 4518 ohm shunt Z at 10 GHz,
>> produces a 49.5 ohm tdr blip for 170 fs (0.9% UI).
>>
>> Conclusions:
>>
>> - There is nothing wrong with the information about square corners
>> found in the RF and Microwave literature. It applies to the wide, low
>> loss
>> traces used in RF design, and is quite correct, corners do matter.
>> - For digital designs traces of 10 mil width or less are generally
>> used, and as such corner design is essentially unimportant, due to the
>> benefit of size scaling on reduction in the size and duration of the
>> discontinuity.
>> - As a figure of merit, I'd suggest we use 5% of UI, and +/- 5% Z0 as
>> the point that we start considering that a particular type of
>> discontinuity
>> matters for SerDes channels. This is conservative, but I like being
>> conservative, and working with positive margin, rather than fighting
>> against
>> negative margin.
>> - Up to 20-ish Gbps, 90 degree CAD layout corners on traces up to 10
>> mil in width have no significant impact on the signal.
>> - At 56 Gbps, 90 degree CAD layout corners become significant
>> starting at 5 mil width.
>> - At 28 Gbps and 56 Gbps designers may be fighting high copper and
>> dielectric losses, forcing the usage of low loss dielectrics (tanD <
>> 0.005),
>> smooth copper foils (surface roughness < 0.4 micron RMS), and wider
>> traces.
>> In these cases, corner mitering, or routing of traces using circular arcs,
>> might be considered, when traces are wider than 10 mil @ 28 Gbps and 5
>> mil @
>> 56 Gbps.
>>
>>
>> Another way to look at corners is from the view of a transmission line
>> with distributed loading. On page 317 of Eric Bogatin's book, he shows his
>> geometric derivation for the computation of corner capacitance. We can
>> reduce his geometry into 3 square cells at a corner, which can be further
>> divided into 6 equal sized triangular sections. One triangular section
>> represents the excess corner capacitance. If we call this the "unit corner
>> cell" then it's clear that corner capacitance represents an increase of the
>> capacitance of the entire cell by 6/5, or 1.2. Knowing this we can compute
>> the distributed Impedance of the line as Z(distributed) = Z0 x sqrt(5/6) >>
>> 0.91 Z0. For 50 ohm impedance, that amounts to a distributed transmission
>> line impedance of 45.6 ohms. So, if we were to cascade corners in a
>> diagonal stairstep fashion, the distributed impedance of the line would
>> asymptotically approach around 45 ohms, since the capacitance becomes
>> averaged across a longer distance. This is independent of the line width.
>> In addition, the distributed delay of the transmission line is increased by
>> sqrt(6/5) or by 1.095, across the unit cell section, or about 16 ps per inch
>> of additional delay for Er=4.
>>
>> So where could we have a problem? Using the distributed version of the
>> analysis, we can see that stair step type structures might accentuate corner
>> capacitance issues. One place where this can happen is in the routing
>> escape pin fields of BGA and connectors. Another is the increase in actual
>> delay that can be seen in trace delay matching serpentine sections. Even if
>> coupling between serpentine sections is minimized, a unit rectangular
>> serpentine section has 4 corners. For 5 mil trace width, each corner has an
>> excess capacitance of 6.3 fF, an incremental delay adder of about 300 fs.
>> For the 4 corners of a serpentine section, there is 1.2 ps of additional
>> delay, not accounted for by net length calculations. Short squarish delay
>> matching sections (so called delay bumps or blips along a line) with 4
>> corners per blip will experience a large percentage increase in delay over
>> the net length calculation vs. longer rectangular delay matching sections,
>> with fewer total number of corners.
>>
>> Real world? It depends on the world you're designing in.
>>
>> best regards,
>>
>> Scott
>>
>>
>> 1. Experimental derivation of optimal miter can be found in: R. J. P.
>> Douville and D. S. James, Experimental study of symmetric microstrip bends
>> and their compensation; IEEE Trans. Microwave Theory Tech., vol. MTT-26, pp.
>> 175-182, Mar. 1978.
>>
>>
>>
>> Scott McMorrow
>> Teraspeed Consulting Group LLC
>> 121 North River Drive
>> Narragansett, RI 02882(401) 284-1827 Business(401) 284-1840 Fax
>> http://www.teraspeed.com
>>
>> Teraspeed® is the registered service mark of
>> Teraspeed Consulting Group LLC
>>
>>
>> On 7/18/2011 10:14 AM, Jack Olson wrote:
>>
>> Speaking from the board designers point of view:
>> I may never understand why people use square corners in their models when
>> they want to experiment with this subject. Are we talking about 90 degree
>> bends? or drawing traces with square corners? Maybe it is interesting from a
>> mathematical point of view, but I've never met a board designer who used
>> square apertures to draw traces. Every modern board design I've ever seen
>> (by modern I mean designed in a CAD system , not the old manual tape
>> layouts) uses round apertures, and when using a round aperture the width is
>> always constant, no matter how you "bend" the trace.
>> Furthermore, I haven't seen too many designs where the bends weren't 45
>> degrees anyway, why would anyone route 90 degree bends? longer runs, in most
>> cases.... but theoretically I suppose its interesting to discuss.
>> Real world? not so much.
>>
>> onward thru the fog,
>> Jack
>>
>>
>> .
>> Date: Fri, 15 Jul 2011 16:56:38 -0400
>> From: Scott McMorrow <scott@xxxxxxxxxxxxx> <scott@xxxxxxxxxxxxx>
>> Subject: [SI-LIST] Re: Right Angle Bends
>>
>> Lee
>>
>> It's not so much "misinformation" but "misapplication" of information.
>> The "no right angle bend rule" makes perfect sense on RF microstrip
>> boards where the traces are about 1 or 2 mm from the plane, and are
>> extremely wide. When you're dealing with 50 ohm traces that are 100
>> mils wide, excess capacitance at the corner is a big deal, since the
>> discontinuity acts for about 140 mils in distance (the diagonal across
>> the corner). If built on an FR4-type material with a Dk = 4, this
>> corner discontinuity has about a 25 ps time duration, which can be
>> significant. Additionally, RF engineers are always trying to reduce
>> narrow band return loss to extremely low levels, far beyond that which
>> is necessary for broadband digital.
>>
>> However, when we scale the traces down to 5 mil width, the discontinuity
>> is same relative size, but 1/20th the physical size, and acts for only
>> about 7 mils, or about 1.25 ps. IF a 1.25 ps discontinuity is a big
>> deal to an engineer then this might matter, or if you have 20 corners,
>> the cumulative effect of this discontinuity will span a duration of 25
>> ps, or 1/4 of a 10 Gbps bit time. But 1.25 ps of excess capacitance
>> does not matter until we designing for 50 Gbps, and only a fool would
>> route a trace with 20 corners in it, so effectively corners are not an
>> issue.
>>
>> Lee, you are correct.
>>
>> Scott
>>
>> Scott McMorrow
>> Teraspeed Consulting Group LLC
>> 121 North River Drive
>> Narragansett, RI 02882(401) 284-1827 Business(401) 284-1840 Fax
>> http://www.teraspeed.com
>>
>> Teraspeed® is the registered service mark of
>> Teraspeed Consulting Group LLC
>>
>>
>> On 7/15/2011 3:15 PM, Lee Ritchey wrote:
>>
>> That is another urban legend. Never been true. I've seen fabricators say
>> this and then etch outer layers with all sorts of surface mount pads that
>> have traces entering them that result in right angle corners and never
>> complain!
>>
>> We'll probably all go to our graves before we flush out all this
>> misinformation!
>>
>>
>>
>>
>
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