[SI-LIST] Re: Rembrandt versus Art Barn
- From: steve weir <weirsi@xxxxxxxxxx>
- To: Joel Brown <joel@xxxxxxxxxx>
- Date: Wed, 08 Apr 2009 17:20:10 -0700
Joel, it's certainly the exception rather than the rule. Intel, and
IBM both provide adequate information at least for certain ICs. Altera
is getting pretty close. I expect they will be there sometime in 2009.
I am hoping to get there sometime this year with certain chips from Micron.
If a manufacturer provides impedance versus frequency profile for power
impedance ( ideally both magnitude and phase ), and a specification for
noise sensitivity, then you can do your job. The first and most
embarrassing question that I think should be directed at each and every
apps dept is: "What metrics are your PDN recommendations based on?"
The corollary question to every sales rep who comes in the door should
be: "I am very interested in using your chip. I won't be able to do
that without basic power delivery metrics. I might consider your chip
without that information if your company will indemnify us for any
losses we suffer due to PDN related problems with your chip."
Many times yes, the PDN recommendations from a chip supplier are total
junk built as assumptions on top of assumptions on top of assumptions.
The "you might just be a redneck if..." is an old schtick of the
comedian Jeff Foxworthy. For instance: "If you go to family reunions
looking for dates, then you might just be a redneck."
My fear for the industry is that sooner or later the barracudas with
briefcases will see the $400 billion per year IC industry and realize
that from a legal standpoint they can readily show that most PDNs are
designed negligently. In most cases, no one from the IC manufacturer to
the OEM can typically show any analysis that the power system is
actually going to work reliably. All they need is some automobile with
Microsoft Vista Embedded Defect Edition, or one of those Skytanic 380s
to be involved in one or a series of crashes and it's going to be a
combination of the tobacco and ADA shakedown lawsuits all over again.
Best Regards,
Steve.
Joel Brown wrote:
> Steve,
>
> I have yet to encounter an IC manufacturer that will give the information
> you stated below. If you know of any can you please list them? In absence of
> such information how could one not at least consider manufacturer
> recommendations of bypass capacitor and ferrite bead configurations?
> Are you saying those recommendations are mostly wrong and worthless?
> We would all like to design a PDN intelligently and knowing all the
> parameters of the IC, pcb, capacitors and ferrites but I am afraid that is
> not real world and in the end we have to make our best guess. I also do not
> understand your use of the term redneck but I don't consider myself one so
> it does not offend me either.
>
> Joel
>
>
> -----Original Message-----
> From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
> Behalf Of steve weir
> Sent: Wednesday, April 08, 2009 3:38 PM
> To: olaney@xxxxxxxx
> Cc: Sol.Tatlow@xxxxxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
> Subject: [SI-LIST] Re: Rembrandt versus Art Barn
>
> Ferrites can be incredibly useful tools. More often than not I see them
> used inappropriately where they do little or no good and introduce nasty
> side effects.
>
> With my apologies to Jeff Foxworthy:
>
> If your IC manufacturer won't tell you the required power rail impedance
> versus frequency at the IC mounting pads, the IC manufacturer might just
> be a redneck.
>
> If your IC manufacturer says place some number of bypass capacitors per
> power pin, the IC manufacturer might just be a redneck.
>
> If your IC manufacturer tells you to use a certain bypass network
> without regard to capacitor placement, mounting method, or PCB stack-up,
> the IC manufacturer might just be a redneck.
>
> If your IC manufacturer tells you to put special features in your PCB
> like moats without specifying the numeric parameters driving that, the
> IC manufacturer might just be a redneck.
>
> If your IC manufacturer tells you to add reactive elements like ferrite
> beads without specifying the network frequency response, the IC
> manufacturer might just be a redneck.
>
> If your IC manufacturer insists that you have to use particular
> practices like a linear regulator, but won't tell you the noise
> susceptibility of their IC, the IC manufacturer might just be a redneck.
>
> If you blindly follow advice from an IC manufacturer without getting
> metrics, you might just be a redneck.
>
>
>
> olaney@xxxxxxxx wrote:
>
>> Perhaps the supplier knows the chip better than anyone else, but when it
>> comes to putting it on PCB and making it play well with others... let's
>> just say that silicon designers often aren't SI or EMC experts by a long
>> shot. I've spent enough time showing semi manufacturers their mistakes
>> and suggesting improvements that I never take a demo board at face value.
>> Some are empirically tweaked beyond all reason to make them work, and
>> sometimes I wonder what they were smoking (a ferrite bead in series with
>> the ground pin of an IC???). Playing monkey see, monkey do with these
>> layouts can get you into real trouble. Others are clearly works of
>> scientific art that I study carefully to see what I can learn. GaAs
>> designers seem to have the knack.
>>
>> The expertise to tell Rembrandt from Art Barn when studying a suggested
>> layout is not in everybody's kit bag. I'd be curious to hear the ways
>> that others distinguish one from the other. One I use is the observation
>> that a classic response to inadequate understanding is an attempt to
>> compensate through overdesign. The result is lots more components in the
>> schematic than experience says should be necessary.
>>
>> Orin Laney
>>
>> On Wed, 08 Apr 2009 18:47:26 +0200 Sol Tatlow
>> <Sol.Tatlow@xxxxxxxxxxxxxxxxxxxx> writes:
>>
>>
>>> Steve, thanks, finally, for an answer.
>>>
>>> As to why one would want to do this, it's very simple:
>>> when the chip manufacturer recommends you do something that
>>> goes against what you believe is right.
>>>
>>> Theoretically, he should know his chip better then anyone
>>> else (right?!?), and the application note should be there
>>> to help 'real-life' engineers implement the chip with
>>> minimal effort. Trouble is, experience tells me this is
>>> often not the case, as you already confirmed, like, I guess,
>>> many others could.
>>>
>>> The 2 variant 'trick' covers you with minimal risks and
>>> costs. This is exactly why I did it in the past, and in all
>>> 3 cases, I was vindicated. Simple, and painless, and not
>>> really a science experiment at all, with all due respect.
>>>
>>> My aim is pretty much the same as yours, I think, to get
>>> customers' designs realised as best I can, and I believe
>>> that in some cases, the 2 variant trick is a handy 'tool' -
>>> granted, not in every case, perhaps, but certainly sometimes.
>>>
>>> Sol
>>>
>>>
>>> steve weir schrieb:
>>>
>>>
>>>> Sol, no and aside from a burning desire to conduct science
>>>>
>>>>
>>> experiments
>>>
>>>
>>>> I don't know why anyone else would.
>>>> I don't what is more real life than real physics. The experiment
>>>>
>>>>
>>> I
>>>
>>>
>>>> proposed to Lee can be implemented as the one panel experiment you
>>>>
>>>>
>>> seek.
>>>
>>>
>>>> Steve.
>>>> Sol Tatlow wrote:
>>>>
>>>>
>>>>> Steve, Charles, thanks for taking time to respond - your comments
>>>>> are all clear and understood... but you still haven't answered
>>>>>
>>>>>
>>> the
>>>
>>>
>>>>> question, or rather, given any real-life examples!
>>>>>
>>>>> Let me rephrase the question once more - and this is not just for
>>>>> you, but for all of those 3,500 people out there who are
>>>>>
>>>>>
>>> subscribed
>>>
>>>
>>>>> to this list, of whom so few responded:
>>>>>
>>>>> Have you ever had 2 variants of the same layout manufactured on
>>>>>
>>>>>
>>> the
>>>
>>>
>>>>> same panel, where the only difference between the two is that one
>>>>> has a solid ground plane, and the other has some form of moating
>>>>> and/or ferrite (or otherwise) isolated ground islands, where one
>>>>>
>>>>>
>>> of
>>>
>>>
>>>>> the variants could be indisputably shown to perform better, with
>>>>> respect either to functionality or EMI? If so, which one?
>>>>>
>>>>> There... that's hopefully now in a form where anyone can easily
>>>>>
>>>>>
>>> and
>>>
>>>
>>>>> quickly give a more or less simple 'yes' or 'no' answer ;)!!!
>>>>>
>>>>> Sol
>>>>>
>>>>> P.S. Troublingly, it seems that a lot of the emails on this
>>>>>
>>>>>
>>> subject
>>>
>>>
>>>>> haven't even reached me... so, sorry if I didn't respond to
>>>>>
>>>>>
>>> anyone,
>>>
>>>
>>>>> assume in that case I didn't get the mail, and try sending it
>>>>>
>>>>>
>>> again.
>>>
>>>
>>>>> (yes, I looked in the 'spam' folder - no sign of them there
>>>>>
>>>>>
>>> either)
>>>
>>>
>>>>> steve weir schrieb:
>>>>>
>>>>>
>>>>>
>>>>>> Sol there are too many variables to give you a single answer or
>>>>>>
>>>>>>
>>> a
>>>
>>>
>>>>>> simple closed formula. If we have enough distance to work with
>>>>>>
>>>>>>
>>> we can
>>>
>>>
>>>>>> obtain arbitrary isolation. Moating comes into play when the
>>>>>>
>>>>>>
>>> amount
>>>
>>>
>>>>>> of distance we have to work with is insufficient. For anything
>>>>>>
>>>>>>
>>> more
>>>
>>>
>>>>>> complicated than the kind of simple demonstration I proposed one
>>>>>>
>>>>>>
>>> is
>>>
>>>
>>>>>> stuck doing the engineering work. If you are looking for a
>>>>>>
>>>>>>
>>> benchmark,
>>>
>>>
>>>>>> a crude one that I can offer is that if you need more than 60dB
>>>>>> isolation, you should be questioning whether this can be
>>>>>>
>>>>>>
>>> packaged
>>>
>>>
>>>>>> compactly without a split.
>>>>>>
>>>>>> Your comments about vagueries in appnotes is well founded.
>>>>>>
>>>>>>
>>> There is
>>>
>>>
>>>>>> no substitute for doing the actual engineering.
>>>>>>
>>>>>> Steve.
>>>>>> Sol Tatlow wrote:
>>>>>>
>>>>>>
>>>>>>
>>>>>>> Steve, no question, I understand and agree. Actually, I was
>>>>>>>
>>>>>>>
>>> hoping
>>>
>>>
>>>>>>> for some real-life examples of when moating (or ferrite
>>>>>>>
>>>>>>>
>>> connected
>>>
>>>
>>>>>>> analog/digital grounds) really has been more or less PROVEN to
>>>>>>>
>>>>>>>
>>> be
>>>
>>>
>>>>>>> a necessary and good idea... and preferably not just eval
>>>>>>>
>>>>>>>
>>> boards,
>>>
>>>
>>>>>>> but 'proper' boards.
>>>>>>>
>>>>>>> As I said, I don't expect a full dissection of anybody's
>>>>>>>
>>>>>>>
>>> private
>>>
>>>
>>>>>>> work - it would be something if I could just hear from a
>>>>>>>
>>>>>>>
>>> handful
>>>
>>>
>>>>>>> of people that they had 2 variants of the same board made at
>>>>>>>
>>>>>>>
>>> the
>>>
>>>
>>>>>>> same time, on the same panel, one with a split ground, and one
>>>>>>>
>>>>>>>
>>> with
>>>
>>>
>>>>>>> a solid ground, where it was found that one was better (in
>>>>>>>
>>>>>>>
>>> whatever
>>>
>>>
>>>>>>> way) than the other.
>>>>>>>
>>>>>>> It's a simple technique, but my suspicion is that noone is
>>>>>>>
>>>>>>>
>>> going to
>>>
>>>
>>>>>>> be able to give me a good CONCRETE case FOR a ground split,
>>>>>>> particularly not with regards to EMI... although I would love
>>>>>>>
>>>>>>>
>>> to be
>>>
>>>
>>>>>>> proved wrong, to know 100% certain that all those painstaking
>>>>>>> efforts I have made in the past on so many boards with split
>>>>>>>
>>>>>>>
>>> planes
>>>
>>>
>>>>>>> really were necessary :)!
>>>>>>>
>>>>>>> Of course, producing and assembling 2 variants of the same
>>>>>>>
>>>>>>>
>>> board is
>>>
>>>
>>>>>>> coupled with higher costs; particularly with prototypes, I can
>>>>>>>
>>>>>>>
>>> also
>>>
>>>
>>>>>>> understand why people, if they only have 5 good chips, don't
>>>>>>>
>>>>>>>
>>> want
>>>
>>>
>>>>>>> to 'risk' even one of them in this way.
>>>>>>>
>>>>>>> Nevertheless, it really irks me to have to follow some app note
>>>>>>> which seems to have little to do with the real world, simply
>>>>>>> because everyone in the design chain was/is too worried of
>>>>>>>
>>>>>>>
>>> having
>>>
>>>
>>>>>>> problems... kind of "Well, the last chip we did was on an eval
>>>>>>> board with a split plane, and THAT worked, so let's do it the
>>>>>>>
>>>>>>>
>>> same
>>>
>>>
>>>>>>> way again", the main target being that the eval board looks
>>>>>>>
>>>>>>>
>>> great
>>>
>>>
>>>>>>> and the chip performs perfectly!
>>>>>>>
>>>>>>> So, let me reformulate my original question:
>>>>>>>
>>>>>>> Have you any real-life examples where the correct use of
>>>>>>>
>>>>>>>
>>> moating
>>>
>>>
>>>>>>> or split DGND/AGND planes (as opposed to one solid ground) on
>>>>>>>
>>>>>>>
>>> an
>>>
>>>
>>>>>>> otherwise well placed and routed board, was 100% shown to "make
>>>>>>>
>>>>>>>
>>> or
>>>
>>>
>>>>>>> break" a product? A simple "no" is of course also a good answer
>>>>>>>
>>>>>>>
>>> :)!
>>>
>>>
>>>>>>> Sol
>>>>>>>
>>>>>>>
>>>>>>> steve weir schrieb:
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>> Sol, unfortunately there is not a single answer. In most
>>>>>>>>
>>>>>>>>
>>> cases
>>>
>>>
>>>>>>>> moating is a bad idea, particularly if one does not understand
>>>>>>>>
>>>>>>>>
>>> the
>>>
>>>
>>>>>>>> caveats and how to deal with them. It's not just the moats:
>>>>>>>>
>>>>>>>>
>>> It's
>>>
>>>
>>>>>>>> the
>>>>>>>> placement, clearances, stitching, and routing that all need to
>>>>>>>>
>>>>>>>>
>>> be
>>>
>>>
>>>>>>>> considered.
>>>>>>>>
>>>>>>>> Steve
>>>>>>>>
>>>>>>>> Sol Tatlow wrote:
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>> I know this subject has been raised before, countless times
>>>>>>>>>
>>>>>>>>>
>>> in one
>>>
>>>
>>>>>>>>> guise or another. I have also googled plenty. I'm not looking
>>>>>>>>>
>>>>>>>>>
>>> for
>>>
>>>
>>>>>>>>> theoretical opinions, either, about whether or not, or when,
>>>>>>>>>
>>>>>>>>>
>>> they
>>>
>>>
>>>>>>>>> should be used (specifically not, "it depends", unless you've
>>>>>>>>>
>>>>>>>>>
>>> got
>>>
>>>
>>>>>>>>> REAL-LIFE examples, for and against!!!).
>>>>>>>>>
>>>>>>>>> This subject raised its head for me in this case due to using
>>>>>>>>> 2 A/Ds as well as 2 D/As, both from Analog Devices, where one
>>>>>>>>> specifies a split plane, the other specifies no split. Now, I
>>>>>>>>>
>>>>>>>>>
>>> am
>>>
>>>
>>>>>>>>> all too wary of relying simply on evaluation boards, where,
>>>>>>>>>
>>>>>>>>>
>>> in
>>>
>>>
>>>>>>>>> general, one layout is done, and if it works, that's how
>>>>>>>>>
>>>>>>>>>
>>> everyone
>>>
>>>
>>>>>>>>> should do it (_without_ comparing 2 different approaches).
>>>>>>>>>
>>>>>>>>> I personally have 3 concrete cases where split gnds had no
>>>>>>>>>
>>>>>>>>>
>>> positive
>>>
>>>
>>>>>>>>> effect on SI, but significantly worsened EMC results (despite
>>>>>>>>> sticking to all the usual guidelines, like no tracks over the
>>>>>>>>> splits, etc.), but I have no concrete case FOR split ground
>>>>>>>>>
>>>>>>>>>
>>> planes.
>>>
>>>
>>>>>>>>> So, what I'm interested in is: does anyone have CONCRETE
>>>>>>>>>
>>>>>>>>>
>>> examples
>>>
>>>
>>>>>>>>> which they would like to share for/against split planes? The
>>>>>>>>>
>>>>>>>>>
>>> kind
>>>
>>>
>>>>>>>>> of thing I mean would be like in one of the cases I had, where
>>>>>>>>>
>>>>>>>>>
>>> I
>>>
>>>
>>>>>>>>> wanted to go against the suggested approach of using a split
>>>>>>>>>
>>>>>>>>>
>>> gnd,
>>>
>>>
>>>>>>>>> and persuaded my customer to pay for 2 variants of the same
>>>>>>>>>
>>>>>>>>>
>>> board
>>>
>>>
>>>>>>>>> on the same manufacturing panel, one with split ground, one
>>>>>>>>>
>>>>>>>>>
>>> with
>>>
>>>
>>>>>>>>> solid ground. Both variants were assembled and tested, with
>>>>>>>>>
>>>>>>>>>
>>> regards
>>>
>>>
>>>>>>>>> to both SI as well as EMC: both were functionally
>>>>>>>>>
>>>>>>>>>
>>> satisfactory; at
>>>
>>>
>>>>>>>>> EMC testing, however, the split-plane bombed out big time,
>>>>>>>>>
>>>>>>>>>
>>> while
>>>
>>>
>>>>>>>>> the non-split sailed through. I like to think that it wasn't
>>>>>>>>>
>>>>>>>>>
>>> due
>>>
>>>
>>>>>>>>> to any screw-ups on my side, that the split ground failed - I
>>>>>>>>>
>>>>>>>>>
>>> am
>>>
>>>
>>>>>>>>> not a newbie to PCB layouts, and, while for sure no
>>>>>>>>>
>>>>>>>>>
>>> professional
>>>
>>>
>>>>>>>>> expert on all areas of SI, I believe I avoided the typical
>>>>>>>>>
>>>>>>>>>
>>> blunders
>>>
>>>
>>>>>>>>> often present in split ground layouts.
>>>>>>>>>
>>>>>>>>> Anyway, my customer was more than happy, but not everyone has
>>>>>>>>>
>>>>>>>>>
>>> the
>>>
>>>
>>>>>>>>> money/time/desire to do as I suggested. So, any 'war stories'
>>>>>>>>>
>>>>>>>>>
>>> to
>>>
>>>
>>>>>>>>> support one or the other approach would be appreciated to
>>>>>>>>>
>>>>>>>>>
>>> help
>>>
>>>
>>>>>>>>> expand my knowledge and understanding of this subject -
>>>>>>>>>
>>>>>>>>>
>>> obviously,
>>>
>>>
>>>>>>>>> we all respect confidentiality, so I'm not looking for
>>>>>>>>>
>>>>>>>>>
>>> circuits,
>>>
>>>
>>>>>>>>> layouts and so on, but I figure many of you must have stories
>>>>>>>>>
>>>>>>>>>
>>> that
>>>
>>>
>>>>>>>>> can be related regarding this subject. Or perhaps some good
>>>>>>>>>
>>>>>>>>>
>>> links
>>>
>>>
>>>>>>>>> to non-confidential 'real-life' examples/studies?
>>>>>>>>>
>>>>>>>>> Regards,
>>>>>>>>> Sol
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>
>>>>>>
>>>>>>
>>>>>
>>>>>
>>>>>
>>>>
>>>>
>>> --
>>> ________________________________________
>>>
>>> Sol Tatlow, M. Eng. (Oxon)
>>> Product Developer
>>>
>>> Pro Design Electronic GmbH
>>> Albert-Mayer-Str. 16
>>> D-83052 Bruckmuehl
>>> Phone: +49 (0) 8062/808-302
>>> PCFax: +49 (0) 8062/808-2302
>>> sol.tatlow@xxxxxxxxxxxxxxxxxxxx
>>> www.prodesign-europe.com
>>> ________________________________________
>>>
>>> Vertretungsberechtigte Geschaeftsfuehrer:
>>> Helmut Mahr, Ulrike Angersbach, Stephan Roeslmair, Dieter Lessenich
>>>
>>> Registergericht: Amtsgericht Traunstein Registernummer: HRB 13 002
>>>
>>> ------------------------------------------------------------------
>>> To unsubscribe from si-list:
>>> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject
>>> field
>>>
>>> or to administer your membership from a web page, go to:
>>> //www.freelists.org/webpage/si-list
>>>
>>> For help:
>>> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>>>
>>>
>>> List technical documents are available at:
>>> http://www.si-list.net
>>>
>>> List archives are viewable at:
>>> //www.freelists.org/archives/si-list
>>> or at our remote archives:
>>> http://groups.yahoo.com/group/si-list/messages
>>> Old (prior to June 6, 2001) list archives are viewable at:
>>> http://www.qsl.net/wb6tpu
>>>
>>>
>>>
>>>
>>>
>>>
>>
>> ____________________________________________________________
>> Click now for low quotes on great group health insurance plans!
>>
>>
> http://thirdpartyoffers.juno.com/TGL2141/fc/BLSrjpTQb2SWNA59vh2Ov5i8j71ZX1Ej
> PP0X3ixmZICTkw42yAj6xKI6DVu/
>
>> ------------------------------------------------------------------
>> To unsubscribe from si-list:
>> si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
>>
>> or to administer your membership from a web page, go to:
>> //www.freelists.org/webpage/si-list
>>
>> For help:
>> si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
>>
>>
>> List technical documents are available at:
>> http://www.si-list.net
>>
>> List archives are viewable at:
>> //www.freelists.org/archives/si-list
>> or at our remote archives:
>> http://groups.yahoo.com/group/si-list/messages
>> Old (prior to June 6, 2001) list archives are viewable at:
>> http://www.qsl.net/wb6tpu
>>
>>
>>
>>
>>
>
>
>
--
Steve Weir
Teraspeed Consulting Group LLC
121 North River Drive
Narragansett, RI 02882
California office
(866) 675-4630 Business
(707) 780-1951 Fax
Main office
(401) 284-1827 Business
(401) 284-1840 Fax
Oregon office
(503) 430-1065 Business
(503) 430-1285 Fax
http://www.teraspeed.com
This e-mail contains proprietary and confidential intellectual property of
Teraspeed Consulting Group LLC
------------------------------------------------------------------------------------------------------
Teraspeed(R) is the registered service mark of Teraspeed Consulting Group LLC
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts: