Eric Bogatin is coming to Silicon Valley, don't miss out his upcoming talk on Four Channel Design Features that Will Open Your Eyes. For registration & more details: Register at http://www.fpgacentral.com/si-techtalk Successful channel design above 5 Gbps does not happen by accident. Four specific signal integrity problems typically contribute to increased deterministic jitter and eye closure. However, these problems can be minimized by identifying their root cause and optimizing the physi-cal design of the interconnects to minimize these prob-lems. In this brief lecture by Eric Bogatin, we introduce the four problems, their root cause and a methodology to optimize channel interconnect design to improve eye quality. These design techniques apply to serial links even above 15 Gbps. Agenda 5:00 - 5:30 PM Registration, Networking & Refreshments 5:30 - 6:30 PM Tech Talk 6:30 - 7:00 PM Q & A Session More details: http://www.fpgacentral.com/si-techtalk ------------------------------------------------------------------ To unsubscribe from si-list: si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field or to administer your membership from a web page, go to: //www.freelists.org/webpage/si-list For help: si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field List technical documents are available at: http://www.si-list.net List archives are viewable at: //www.freelists.org/archives/si-list Old (prior to June 6, 2001) list archives are viewable at: http://www.qsl.net/wb6tpu