[SI-LIST] RapidIO timing
- From: Steve Horne <sch@xxxxxxxxxxxxxx>
- To: james.f.peterson@xxxxxxxxxxxxx
- Date: Mon, 28 Mar 2005 10:08:39 -0600
You are correct that the shifting is expected to be done in the
receiver. The transmitter spec has the clock and data closely
aligned.
There is a defined training protocol that provides a pattern for
the receiver to train itself on. This training is not required
for lower frequencies, but is needed at about 1Gbps and above
(depending on various things). Additionally, there is logical and
physical layer error recovery behavior that deals with a receiver
that has lost "lock".
The RapidIO specification is probably your best source of
information, but it can be confusing in places.
Steve
Peterson, James F (FL51) writes:
> I'm a little confused with the timing of RapidIO.
>
> At some point before the receiving flop the source synchronous clock or data
> must be shifted in order to allow for setup and hold time.
>
> Theoretically, this shifting can be done at the transmitter, on the board,
> or at the receiver.
>
> The part I'm confused with is that the RapidIO requirement seems to limit
> this shifting to the receiver only. I'm basing this on the receiver
> "Tskew,pair" parameter and the way that it's defined in figure 8-8 of the
> spec ("Data to Clock Skew"). A close look at this rule implies a very
> aligned clock edge and data edge (if I'm reading it correctly). In order to
> meet this, the shift must be done afterwards.....
>
> Can one of you RapidIO wizards help clarify this?
>
> Also, I'm looking for a good paper on this subject (Receive clocking of
> RapidIO).
>
> thanks,
> Jim Peterson
> Honeywell
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- References:
- [SI-LIST] RapidIO timing
- From: Peterson, James F (FL51)
Other related posts:
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- [SI-LIST] RapidIO timing
- From: Peterson, James F (FL51)