[SI-LIST] Re: REPOST: SI Question 1 of 3: "Quiet" lines over split in ground plane

John-Paul, the slot will get excited by energy in a line that crosses 
it.  You won't get the kind of amplitude that a live signal would have, but 
you will have whatever noise exists between the domains continue to excite 
those slots.  But the more interesting question is what the return path 
looks like for the SPI clock when you are trying to use it.  You might want 
to use a little drawbridge made from digital ground.

Regards,


Steve.
At 09:32 AM 10/31/2005 +0000, John-Paul Coetzee wrote:

>Reposted to try and make the diagram clearer!
>
>I am working on a telecoms design with Analog and Digital areas.  The =
>whole unit is inside a thick metal box, with the PCB bolted and grounded =
>to the chassis across the board.  Various parts of the PCB are also =
>further isolated by slots in the ground and power planes and also by =
>walls bolted to exposed ground plane on the top and bottom of the board.
>
>Here is an ASCII picture of small part of the board showing a digital =
>area, analog area, the slots isolating those areas and the soild metal =
>wall. You will only be able to see this picture properly in monospaced =
>font
>
>There are 3 SPI serial data and clock lines crossing into the analog =
>zone.  These are only active in the first few seconds after power-up =
>after which they are held low.
>
>What are the risks of these "quiet" signals crossing the slot?
>
>|                        #########    D I G I T A L   G R O U N D
>|                        #########
>|               +-------+#########       +-----------------------
>|               |       |#########       |             =20
>|               |       |#########       |         S L O T      =20
>|               |       |###   ###       |             =20
>|               |   S   |### W ###       +-----------------------
>|               |       |###   ###      =20
>|               |   L   |### A ###      =20
>|               |       |###   ###
>|               |   O   |### L ###
>|               |       |###   ###
>|               |   T   |### L ###     A N A L O G   G R O U N D
>|               |       |###   ###
>|               |       |#########
>|               |       |#########
>|    --------------------#########------------->------- SPI Clock
>|               |       |#########
>|    --------------------#########------------->------- SPI Data
>|               |       |#########
>|    --------------------#########------------->------- SPI LE
>|               |       |#########
>|               |       |#########
>|               |       |#########
>|               |       |#########
>|               |       |#########
>|               +-------+#########
>|                        #########
>|                        #########
>|                        #########
>+----------------------------------------------------------------
>
>
>--
>JP Coetzee  (was JP Nicholls) /  jpcoetzee@xxxxxxxx
>
>Digital Design Engineer
>
>Powerwave UK Ltd
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