[SI-LIST] Re: R: Re: R: digital core model

Thanks a lot for the suggestion. But can you suggest anything other than
transistor-level  model? What do you think of a kind of norton equivalent
current model which basically a current source in parallel with capacitor,
and then using triangular shape current waveform?
I used to get support from Ansoft in UK. I don't remember if we were ever in
contact.

saoer

On 11/29/06, gianguida@xxxxxxxx <gianguida@xxxxxxxx> wrote:
>
> If you have a really good circuit simulator
> able to analyse very large netlist in a resonable
> amount of time
> the combined usage of transistor level model for the die
> and em simulation ( 3D in my personal opinion)
> to model the interconnection will give you
> the best results
> Giancarlo
>
> P:S: did we exchange some email... time ago when I worked for Ansoft?
>
>
> -----Messaggio originale-----
> Da: si-list-bounce@xxxxxxxxxxxxx per conto di Saoer Sinaga
> Inviato: mer 29/11/2006 14.31
> A: si-list@xxxxxxxxxxxxx
> Oggetto: [SI-LIST] Re: R: digital core model
>
> Dear Giancarlo,
> Thanks for the reply.
> I would like to do something like SSN simulation, also try to optimize my
> PDN.
> I have resources to do EM simulation (2D, 2.5D, 3D), circuit simulation,
> etc.
>
> saoer
>
>
> On 11/29/06, gianguida@xxxxxxxx <gianguida@xxxxxxxx> wrote:
> >
> > dear Saoer,
> > the answer to your question
> > depends on
> > 1) what effects you need to model
> > 2) what simulation resources you have to use the model
> > 3) what is the accuracy you need to achieve
> > may be you may want to better specify your needs.
> >
> > Regards
> > Giancarlo
> >
> > -----Messaggio originale-----
> > Da: si-list-bounce@xxxxxxxxxxxxx per conto di Saoer Sinaga
> > Inviato: mer 29/11/2006 10.25
> > A: si-list@xxxxxxxxxxxxx
> > Oggetto: [SI-LIST] digital core model
> >
> > Hi all,
> > I want to do System in Package modeling. The SiP is laminate based,
> > and consists of several active silicon dies. What kind of model should I
> > use
> > for those active dies? Should I use transistor-level model? or should I
> > use
> > the current profile information? or just a simple norton equivalent core
> > model?
> >
> > Anyone could give me an idea? or perhaps refer some papers or books?
> >
> > thanks a lot,
> > Saoer
> >
> >
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