[SI-LIST] Re: R: Re: Impedance deviation due to prepreg shrinking
- From: Robert Haller <rhaller@xxxxxxxxxx>
- To: "Russell D. Moser" <r.moser@xxxxxxxxxxxxxxxxx>
- Date: Mon, 11 Jul 2005 15:45:48 -0400
(Open door for DesignCon East plug)
Yes, In fact Scott McMorrow and Chris Heard have a paper " the Impact of
PCB laminate
Weave on the Electrical Performance of Differential Signaling at
Multi-Gigabit Data Rates"
6-TA3
http://www.iec.org/events/2005/designcon_east/conference/schedule_track.html
regards,
Bob
Russell D. Moser wrote:
>I think that there was some good work done on this issue incidental to
>DESIGNCON. Go to their WEB archives and search.
>
>Regards,
>___________________
>Russell D. Moser
>Founder and CEO
>Orion Group
>r.moser@xxxxxxxxxxxxxxxxx
>www.theoriongroup.net
>US Phone: 717.914.0116
>US Facsimile: 717.704.0051
>
>
>
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>-----Original Message-----
>From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
>On Behalf Of Robert Haller
>Sent: Monday, July 11, 2005 1:00 PM
>To: Carlo_Franco.Bleu@xxxxxxxxxx
>Cc: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: R: Re: Impedance deviation due to prepreg
>shrinking
>
>Carlo, and engiz,
> Practically speaking cores and prepregs are different. Cores are
>partially cured laminate while prepregs are uncured laminate.
>The glass/resin content can (and does) vary. The Dielectric Constant
>between cores and prepregs can (and does) vary.
>Depending on your application, (frequency, edge rate) it may be a small
>effect. Papers and data are available from laminate suppliers and in
>trade journals.
>
>Regards,
>Bob Haller
>Principal Consultant
>Signal Integrity Software Inc.
>
>Bleu Carlo Franco wrote:
>
>
>
>>Cengiz,
>>theoretically speaking, when you define the thickness of dielectric, =
>>prepreg or core, you ask to your customer for the value after the =
>>pressing phase. So you do not care if the dielectric is core or
>>prepreg, = it is your customer problem how much thick is the initial
>>prepreg to = obtanin the wanted final thickness.
>>
>>Hope this help
>>Carlo
>>
>>-----Messaggio originale-----
>>Da: steve weir [mailto:weirsi@xxxxxxxxxx]
>>Inviato: luned=EC 11 luglio 2005 11.35
>>A: caydin@xxxxxxxxxxxxxxxxx; si-list@xxxxxxxxxxxxx
>>Oggetto: [SI-LIST] Re: Impedance deviation due to prepreg shrinking
>>
>>
>>Cengiz, yes the material varies. This is an issue that addresses the =
>>
>>
>
>
>
>>skill=20 and experience of the board fabricator. An experienced shop
>>will be = able=20 to adjust the unpressed stack thickness and copper
>>line width so that = after=20 pressing good impedance control is
>>maintained when the stack-up is=20 reasonable to begin with.
>>
>>Steve.
>>
>>
>>At 12:28 PM 7/11/2005 +0000, caydin@xxxxxxxxxxxxxxxxx wrote:
>>
>>
>>
>>
>>
>>>Dear listl,
>>>
>>>How prepreg layers effect the impedance of a stripline? To clarify, my
>>>
>>>
>
>
>
>>>stack-up is;
>>>
>>>S1
>>>-------------- core
>>>--------------
>>>GND
>>>-------------- prepreg
>>>--------------
>>>S2
>>>-------------- core
>>>--------------
>>>VDD1
>>>-------------- prepreg
>>>--------------
>>>S3
>>>-------------- core
>>>--------------
>>>GND
>>>-------------- prepreg
>>>--------------
>>>S4
>>>-------------- core
>>>--------------
>>>VDD2
>>>-------------- prepreg
>>>--------------
>>>GND
>>>-------------- core
>>>--------------
>>>S5
>>>
>>>We assume that pcb cores are hard enough to achieve the required line
>>>impedances.
>>>But, how about the impedances for the striplines with one core and one
>>>
>>>
>
>
>
>>>prepreg layer as neighbours, such as GND-S2-VDD1. Is there a rate of
>>>deviation after pcb manufacturing due to prepreg shrinking? Is not it
>>>more problematic if we have multiple core and prepreg layers?
>>>
>>>Any comments, suggestions? Thank you.
>>>
>>>Cengiz Aydin
>>>Researcher
>>>Bilkent University
>>>
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