[SI-LIST] Re: Questions on Reference Planes for DDR3 signals

Steve,

Let's leave out the component/PCB interface for now and consider a 
simple 3-conductor flat ribbon cable for the transmission line 
connecting the TX to the terminations. The center conductor is the 
signal, Vdd and Vss one on each side of the signal. Signal/Vss and 
Signal/Vdd each having a characteristic impedance of 100 ohm.

Do you agree that the above transmission line when used in the SRS 
configuration I described will result only in DC draw from the supply?

I am not sure what you mean by  continuous transmission line signaling 
system but the properties you describe seem to apply to what I described 
as SRS.

If we define SSN as noise caused when multiple buffers/terminations 
share a common PDN impedance, SRS will avoid this noise.

If we now compare the practical implementation of conventional signaling 
and SRS, the question becomes how much of the margin we gained from the 
lack of SSN do we have to give up. The answer will determine if SRS is 
useful in practice.
In conventional signaling we try to keep a constant signal/Vss impedance 
end-to-end. In SRS we have do that for Signal/Vss and Signal/Vdd.

Thanks,
Vinu


On 07/02/2012 06:28 PM, steve weir wrote:
> Vinu, the problem is this:  At the boundary of the component to the PCB,
> the signal forms two transmission lines that each carry the same
> polarity transitions with respect to each of the image planes.  That
> transition carries through the shared impedance of each of the
> respective rails between the package and the PCB.  Voltage developed
> across those shared impedances is the stuff that SSO is made of.
>
> I think that you have confused this configuration with the notion of a
> continuous transmission line signaling system.  In a continuous
> transmission line signaling system the DC current is constant and
> hypothetically, the AC current approaches zero.  An ideal differential
> signaling system has that behavior.  In such a system, signaling is done
> by changing the current distribution between lines, but not the total
> current.  If the lines are all close together then the approximation to
> the ideal can be pretty good.  But that is a very different beast than
> what I believe you have been describing.
>
> If we want to approach zero AC current in the power distribution
> interconnect, then the even mode signal current must approach zero.
>
> Best Regards,
>
>
> Steve.
> On 7/2/2012 5:05 PM, Vinu Arumugham wrote:
>> Steve,
>>
>> May be we should temporarily set aside practical considerations. If you
>> had an SRS configuration with three wires, Vddq/signal/Vss, do you agree
>> that it will steer current and only draw DC from the supply? In contrast
>> any other configuration would draw pulsed current from the supply.
>>
>> Thanks,
>> Vinu
>>
>> On 06/27/2012 06:53 PM, steve weir wrote:
>>> Vinu, there seems to be some discussion at cross purposes going on.  If
>>> we reference a signal to two different planes then the coupled energy
>>> has to make it end to end.  At the die launch we can rely on die
>>> capacitance to provide the necessary driver coupling.  Then under a
>>> first assumption that we approximate equal coupling between each signal
>>> and both rails, and that we introduce only equal inductance between the
>>> die Vddq, and Vss through the package and into the PCB, we can then turn
>>> our attention to the PCB part of the channel.  And this is where it
>>> looks like we are having multiple conversations.
>>>
>>> Let's start with a simple case where there is a single stripline
>>> cavity.  The signal energy that we launch into that cavity will excite
>>> it.  The cavity once excited will resonate at modal frequencies.  If we
>>> want to drive those frequencies up, then we can beak the cavity up into
>>> smaller effective cavities, smaller beer cans if you will by stitching.
>>> Because the two rails require DC isolation, we cannot stitch with vias
>>> that connect the two planes together.  We will have to stitch through
>>> capacitors, which today means returning all the way to the surface and
>>> back with vias.  If the cavity is in the middle of an .062 PCB and we
>>> use regular MLCCs then we are talking about 1nH or more loop inductance
>>> per capacitor.  For signals with 100ps Tr, which has an Fknee near 3GHz,
>>> those capacitors look like 20 Ohms or so.  In order to look like a low
>>> impedance compared to the cavity necessary to affecct the resonances, we
>>> are going to need a lot of capacitors densely packed.  If we don't tame
>>> the resonances, then signals that excite them get the favor returned by
>>> the resulting voltages coupling back into the signals, as well as
>>> setting up EMI headaches.
>>>
>>> Now, if we take the same stripline and make both planes Vss, then we can
>>> stitch together with vias.  The resulting impedance  will be much lower,
>>> as well as the required real estate per short.  One via effects a short
>>> instead of a via pair throughout the PCB, in addition to the surface
>>> area of the bypass caps.  It's a completely different and far more
>>> manageable problem.
>>>
>>> Best Regards,
>>>
>>>
>>> Steve
>>> On 6/27/2012 4:38 PM, Vinu Arumugham wrote:
>>>> I was talking about reducing injection by providing return vias for both
>>>> planes, not about suppression.
>>>>
>>>> Thanks,
>>>> Vinu
>>>>
>>>> On 06/27/2012 01:16 PM, Scott McMorrow wrote:
>>>>> Vinu,
>>>>>
>>>>> sorry, wrong answer.
>>>>>
>>>>> So, one vss via dangling in the cavity
>>>>> One vdd via dangling in the cavity
>>>>> how is the AC short necessary to suppress cavity waves made?
>>>>>
>>>>> you have wrong ideas regarding what a via can do when only connected
>>>>> to one net.
>>>>>
>>>>> Scott
>>>>>
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