[SI-LIST] Re: Questions on Reference Planes for DDR3 signals
- From: Hirshtal Itzhak <ihirshtal@xxxxxxxxxx>
- To: "'weirsi@xxxxxxxxxx'" <weirsi@xxxxxxxxxx>, "si-list@xxxxxxxxxxxxx" <si-list@xxxxxxxxxxxxx>
- Date: Mon, 25 Jun 2012 13:49:01 +0000
I would like to thank to anyone who contributed to help me
Itzhak Hirshtal
-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] On
Behalf Of steve weir
Sent: Saturday, June 23, 2012 7:05 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Questions on Reference Planes for DDR3 signals
Vinu, a completely balanced transmission path can theoretically divide
SSO in half. It does not cancel it. Let us suppose that we have a
completely balanced transmission path using a symmetrical stripline all
the way back to the die launch. For a given di/dt * N bits
transitioning from low to high, relative to BOTH planes the di/dt is
positive. If the interconnect is completely symmetrical then we have
half the total inductance and half the SSO amplitude. We do not cancel
the SSO. The only way to cancel SSO is to code such that the summation
of transitions multiplied by polarity equals zero.
Steve.
On 6/22/2012 10:08 AM, Vinu Arumugham wrote:
> Steve,
>
> A network DRAM package we looked at had signal lines referenced to both
> Vddq and Vss. It also had a pinout where the data pins were interspersed
> with Vddq and Vss.
>
> If the DDR3 DRAM package routing is symmetrically referenced to
> Vddq/Vss, it enables construction of a signal path that is symmetrically
> referenced end-to-end (non-DIMM applications). Along with the fact that
> data lines are thevenin terminated to Vddq/Vss, it creates a special
> signaling configuration where theoretically SSO would be zero.
>
> Thanks,
> Vinu
>
> On 06/21/2012 09:23 PM, steve weir wrote:
>> Vinu this was the practice with the last packages I looked at several
>> years ago.
>>
>> Steve
>> On 6/21/2012 9:49 AM, Vinu Arumugham wrote:
>>> Steve,
>>>
>>> Have you verified that memory packages reference data lines only to Vss?
>>> The memory pinout suggests that data lines are referenced to both Vss
>>> and Vddq.
>>>
>>> Thanks,
>>> Vinu
>>>
>>> On 06/21/2012 01:39 AM, steve weir wrote:
>>>> Hirshtal, this all amounts to reducing signal disturbance.
>>>> Unfortunately, this is another case of: "It all depends." The data
>>>> signals constitute the higher data rates as well as the greater number
>>>> SSOs, so they deserve more care than the A/C signals. However, if you
>>>> want reliable operation at speed, reasonable care must be employed with
>>>> both. You have a few basic options:
>>>>
>>>> 1. Follow a proven topology exactly as though your life depends on it.
>>>> Pray that the gods of reference designs will reward your dedicated
>>>> obedience by blessing your effort.
>>>>
>>>> 2. Develop and evaluate design rules that are suitable to your
>>>> particular situation. Tool sets are available to evaluate different
>>>> topologies, such as from Si-Soft. If you don't have the tools, the
>>>> budget, or the time, then you can lean on an outside service to do this
>>>> for you.
>>>>
>>>> 3. Try to develop rules ad-hoc without checking and hope that Murphy
>>>> does not decide to amuse himself at your expense. The more conservative
>>>> the rules you set, the more likely you can save yourself the wrath of
>>>> Murphy.
>>>>
>>>> Slides 14 and 15 of this presentation available on my web-site
>>>> illustrate what you face with different routing topologies:
>>>> http://www.ipblox.com/pubs/SVCEMC_May_2005/capacitor_placement_public_b.pdf
>>>>
>>>> A couple of comments: Memory packages and DIMMs reference data lines to
>>>> Vss. DIMMs reference A/C to VDDQ. This was done to support low layer
>>>> count PCBs. It works. You will avoid introducing extra noise and
>>>> cross-talk by extending those references in your channel end to end.
>>>> What your memory controllers reference varies. Any reference change you
>>>> introduce will inject energy between the the references used. This can
>>>> be handled, but requires work and more analysis. And unless the design
>>>> is low performance, it usually imposes more cost for equal performance.
>>>>
>>>> A final note: Always treat clock with the utmost care. Barring some
>>>> terrible cost impact a continuous Vss reference is a good way to treat
>>>> clocks.
>>>>
>>>> Steve
>>>> On 6/21/2012 1:42 AM, Hirshtal Itzhak wrote:
>>>>> Hello all,
>>>>> I've been looking at DDR3 layout guides from Micron and from some
>>>>> manufacturers of DDR3 controller devices and haven't found a clear
>>>>> recommendation for how to deal with the issue of reference planes for
>>>>> DDR3 interfaces in a stripline configuration. Also, there are some other
>>>>> "reference-plane" issues which I hope someone can clarify.
>>>>>
>>>>> So here are the questions I haven't found a clear answer for:
>>>>>
>>>>> (1) Almost all recommendations that I've found
>>>>> are to route data-group signals "adjacent to a solid GND Layer". Can I,
>>>>> therefore, route them adjacent to both a GND and a Power plane in a
>>>>> stripline configuration? Does it matter if the stripline is symmetric
>>>>> (relative to the 2 ref planes) or not?
>>>>> (2) Almost all recommendations that I've found
>>>>> are to route address/command/control signals "adjacent to a solid Power
>>>>> or GND Layer". Can I route them adjacent to a Power plane with a voltage
>>>>> different than the DDR3-1.5Volt VDD?
>>>>> (3) If DDR-VDD is required, can I use another
>>>>> solid Power plane as the other plane in stripline configurations
>>>>> (provided the 1st plane is VDD)?
>>>>> (4) What reference plane is recommended for the
>>>>> Clock pair? Micron, for example, doesn't say anything on this matter, but
>>>>> some other manufacturers recommend using only a GND plane. Is this true,
>>>>> as far as you know?
>>>>>
>>>>> Thanks in advance for your help!
>>>>>
>>>>> Itzhak Hirshtal
>>>>> Elta Systems
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