[SI-LIST] Questions about 64b/66b scrambling polynomial

Hello everyone,

I'm doing some research on baseband coding with regards to 10 Gb/s Ethernet, 
having read the patent titled DECODING METHOD AND DECODER FOR 64B/66B CODED 
PACKETIZED SERIAL DATA,I learnt much about the concept of 64b/66b block coding, 
but something about the scrambling method puzzled me. The scrambling polynomial 
chosen here is 

x58+x19+1, together with 3 reasons citing here:

   the chosen polynomial must cause no violations of the Ethernet-standard 
CRC32 coding under exhaustive three-error tests with spill-in and spill-out for 
all packet sizes;

   the polynomial tap spacings must be greater than eight to prevent error 
multiplication from degrading the Hamming distance among the TYPE words; and

   the polynomial order should be>57 to prevent malicious jamming and <64 to 
minimize implementation complexity.

My puzzles are corresponding to the above reasons:

  1¡¢How to prevent the scrambling polynomial from causing violations of the 
CRC32 coding?

  2¡¢The polynomial tap spacings must be greater than 8 to prevent error 
multiplication from degrading the  Hamming distance among the TYPE words, and 
why it is 8 that can prevent error multiplication? 

  3¡¢Why choosing the order of the polynomial as big as 58(or 65), and what is 
"malicious jamming"? 

 

  Thank you very much!

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