[SI-LIST] Question regarding thermal layers
- From: Dennis Tomlinson <det_werks@xxxxxxxxxxxxx>
- To: si-list@xxxxxxxxxxxxx
- Date: Sun, 10 Aug 2003 04:27:22 -0700 (PDT)
I am designing a conductin cooled module which will employ thermal layers in
the stackup and underfill on selected devices. The thermal layers are DC
isolated from circuit ground. I am proposing the following stackup:
1. Signal + Comps
2. Thermal
3. Ground
4. Signal
5. Signal
6. Ground
7. Signal + Area Fills (1.8V, +5V)
8. Signal + Area Fills (-5V, 2.5V)
9. Power (3.3V)
10. Signal
11. Signal
12 Ground
13. Thermal
14 Signal + Comps
My question is in regard to using the thermal layers as signal returns. The
dielectric between thermal and ground layers is 5 mil core. I am contemplating
the use of some strategically placed bypass caps between thermal and ground
layers, as well as between thermal and 3.3V layers. Anyone care to critique or
comment on this plan? Would it make sense to swap layers 9 (3.3V) and 12
(Ground)? Thanks in advance,
Dennis Tomlinson
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