[SI-LIST] Question on SPI/SFI-5

From: "Buchs, Kevin J." <buchs.kevin@xxxxxxxx>
To: si-list@xxxxxxxxxxxxx
Date: Tue, 7 Jun 2005 12:50:53 -0500

In doing some simulations with SPI-5 (3.125 Gbps differential) signals we
are left with a couple of questions the specifications leave unanswered.  We
are reading the SxI-5 specification found here:
http://www.oiforum.com/public/impagreementsum.html .

Does someone else have ideas on these questions from their own work with
SPI-5 or other sources of knowledge:
  1. What are typical driver amplitude and common mode targets?
  2. Is there any provision for pre-emphasis?  It seems the allowable
amplitude margin is tiny, so any p.e. step needs to be small.
  3. Figure 6 gives reference planes for the requirements, but are these are
at the die, package or PCB level?

If anyone would care to point me to an existing transmitter model, that
would be wonderful.  Generic/PWL is fine.  

Thanks

Kevin Buchs   Mayo Foundation  200 1st St. SW  Rochester, MN 55901
buchs.kevin@xxxxxxxx  507-538-5459 http://www.mayo.edu/sppdg 
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[SI-LIST] Question on SPI/SFI-5

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