[SI-LIST] Re: Question on PLL for Data/Clock Recovery Apps
- From: steve weir <weirsp@xxxxxxxxxx>
- To: lmiller@xxxxxxxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Tue, 11 Dec 2001 14:22:28 -0800
Larry,
I think you misread Ed's post.
Ed has it right on all points. Phase is the integral of frequency,
frequency, or angular velocity is the derivative of phase.
I believe that Ed was discussing the fact that the loop imposes a short
term frequency error of opposite sign ( ave ) to the phase error in order
to correct phase errors. In the long term this forces the average
frequency error to zero. I believe that Ed tried to make clear that this
frequency shift isn't a problem. Rather, it's a necessary part of the
solution of maintaining phase alignment.
On the cycle skipping issue, even with a PFD, Ed is again correct. If the
loop bandwidth is insufficient for the incoming disturbance, even using a
PFD, cycle skipping of one or more cycles will occur. This is a good
reason not be careful with, or just avoid VCO based oscillators with high
division ratios: power supply disturbances can lead to unwelcome surprises.
Regards,
Steve.
At 08:35 AM 12/11/2001 -0800, you wrote:
>You are getting some incorrect advice here. See below.
>
>Larry Miller
>
>-----Original Message-----
>From: Ed Miguel [mailto:emiguel@xxxxxxxxxx]
>Sent: Tuesday, December 11, 2001 7:53 AM
>To: si-list@xxxxxxxxxxxxx
>Subject: [SI-LIST] Re: Question on PLL for Data/Clock Recovery Apps
>
>
>Krishnan,
>I think you have to go back and look at the PLL as a PHASE locked loop and
>switch out of the frequency domain which is where your concerns for
>accuracy lie. Look at the basic elements of a PLL, first there is a PHASE
>detector. Any phase error will get translated through this which will
>include jitter, reference movement and VCO noise and movement. This phase
>information will then get filtered, into average phase error, that will
>then be used to control the VCO. Since the PLL is usually a PI
>(proportional/integral) closed loop servo system, the output VCO frequency
>will be adjusted but only enough to zero the phase error. Remember that
>phase is an integral of frequency.
>
>----->>>Phase is the DERIVATIVE of frequency! Ed has it backwards.
>
>
>The response of the PLL is described
>in the gain of the loop as well as the zeta or damping factor. A PLL will
>typically not dwell out of frequency for a while but it will operate
>according to its loop transfer function. If anything it will be slow to
>respond because of the filtering. Of course this is true for the
>condition where the S/N is not so low that the signal is buried in noise
>(jitter) because under those conditions cycle skipping can occur. It also
>assumes that the noise is gaussian. If it is not then it will be treated
>as a phase transient and that will cause the PLL to follow the phase of
>transient (to zero it out) and in the process of doing that it may appear
>to shift in frequency for a while until it gets there. Finally (I think)
>the PLL in acquisition is non-linear so there will be some frequency
>shifting taking place until it gets frequency locked at which point the
>phase error takes over the control.
>
>----->>> You have to achieve frequency lock before you can phase lock. If
>you are off frequency the PLL will cycle skip and is useless. Old phase
>detector designs did this and had a tendency to lock onto sub-harmonics of
>the reference signal (i.e., integral fractions of it like half). Any PLL
>phase detector that is worthwhile these days will keep its error output
>driving to eliminate the frequency error before it drops in the slot on
>phase.
>
>
>You raise some interesting questions and it is something that we all go
>through trying to visualize the operation of a PLL so you are not
>alone. There are some good books on PLL's that you can search for under
>Phase Locked Loops or PLL's by Gardner or Wolaver or Egan or Encinas and
>there are some good Ap Notes out there on the Web. In general I would
>say, look at the transfer function and note the response of the loop as a
>function of zeta, the damping factor. This define how a PLL will typically
>respond.
>
>Ed Miguel
>Engineering Manager of TPG products
>Connor Winfield Corp.
>
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