[SI-LIST] Question on DDR3 specs
- From: "Moreira, Jose" <jose.moreira@xxxxxxxxxx>
- To: <si-list@xxxxxxxxxxxxx>
- Date: Wed, 14 Nov 2007 07:32:23 -0600
Hi,
As anyone looked on the JEDEC DDR3 jitter specs?
I'm a bit confused with the fact that they define all jitter components =
that the clock input must tolerate has Gaussian (period jitter, cycle to =
cycle jitter ,etc...) but they specify the values has being measured on =
200 consecutive cycles and not has Gaussian standard deviations values.
Does anyone have an insight on why the jitter tolerance specs on the =
clock are defined this way?
Thanks in advance
Jose
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List technical documents are available at:
http://www.si-list.net
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
- » [SI-LIST] Question on DDR3 specs
