[SI-LIST] Re: Question about SSTL Termination

Regarding your voltage swing, I suspect that what you are 
seeing is drive strength limitations of the driver.  If you
divide the voltage differences between the drive level and 
Vtt by the termination resistor, you will probably find the 
rated drive strength of the buffer.  Once the low terminator 
is removed, the driver can drive to the rails.

best regards,

MG

-----Original Message-----
From: Aubrey_Sparkman@xxxxxxxx [mailto:Aubrey_Sparkman@xxxxxxxx]
Sent: Tuesday, January 15, 2002 2:03 PM
To: arsenault_brian@xxxxxxx; si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Question about SSTL Termination



Brian,
Actually this does make sense.  A 50 ohm resistor to the Vtt of 1.25 Volts
is NOT a pull-up, but a "pull to center". So your swing to each rail is
loaded equally and you are seeing that the pull-up and pull-down drive
strengths aren't equal.

And my GUESS is that you can use a series termination in some cases, but
YOUR SIMULATIONS should guide your decision.

Good Luck,
Aubrey Sparkman 
Signal Integrity 
Aubrey_Sparkman@xxxxxxxx 
(512) 723-3592



-----Original Message-----
From: arsenault, brian [mailto:arsenault_brian@xxxxxxx]
Sent: Tuesday, January 15, 2002 12:50 PM
To: 'si-list@xxxxxxxxxxxxx'
Subject: [SI-LIST] Question about SSTL Termination




Folks...

I'm working on a design within our company that is utilizing SSTL buffers.
We are working with a semiconductor vendor to add these buffers in as
selectable vs. LVTTL.  Since we are in the definition stage, we also
requested that the termination needed for SSTL be built internal to the
device, reducing the number of external discrete components.  As a note, we
are looking at SSTL2...

One question that came up was, 'Do we really need the pullup resistor (50
ohms to a Vt of 1.25V) or can we live with just the series terminator?'.
The simulations I have run with the pullup indicate a clean signal that
swings between 600mV and 1.8V.  When I remove the pullup, the signal now
swings between 0V and 2.5V.

My question is, does this make sense?  I have tried models from two
different vendors (Xilinx and LSI Logic).  After reading the JEDEC spec on
SSTL, and also the vendor datasheets, I can't come up with an explaination.

Appreciate the help.

Brian

Brian Arsenault
Sr. Signal Integrity Engineer
EMC Corporation
Hopkinton, MA 01748

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