[SI-LIST] Re: Query on power noise sensitivity measurement problem

Greetings,

Here's a link to a recent seminar which covers TX/RX PLL =
characterization. http://www.techonline.com/learning/webinar/206801021=20

This measurement technique would also allow measurement of the Jitter =
Spectrum (RJ/PJ RJ/SJ) while injecting "power noise on PLL power".=20

Best regards,
Rob Sleigh
Digital Test Division
Agilent Technologies, Inc.

-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx] =
On Behalf Of Huang chunxing
Sent: Saturday, April 26, 2008 2:02 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Query on power noise sensitivity measurement problem

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Hi experts,

I am trying to find out whether it is possible to get the relationship =
between powernoise and output jitter by measurement.
To be convenient, I would like to call it Power Noise sensivity. =20

My initial thought is to inject a certain frequency power noise on PLL =
power, and then measure SJ at the frequency on TX output signal.=20
But it is some difficult to be applied in practice due to PDN impedance =
variance.
Is there any craft method to avoid it?

As to RX side, it is difficult to loop out clock recovered by CDR.
I was ever been told that as TX and RX share same PLL, or use same =
design PLL, so power sensitivity at RX is similar with power sensitivity =
at TX. If we measure power sensitivity at TX, then we can get one at RX.
Is that true, or could stand at most cases?

I tried to find some documents for reference, but I failed.
I hope experts here who ever did similar work may give me some comments =
and suggestions.
Thanks in advance! =20


Regards,

Huang Chunxing
HUAWEI TECHNOLOGIES CO.,LTD. =20


Address: Huawei Industrial Base
Bantian Longgang
Shenzhen 518129, P.R.China
Tel: +86 755 89651027
Fax: +86 755 89650600
E-mail: huangchunxing@xxxxxxxxxx
www.huawei.com



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