[SI-LIST] Re: Query on power noise sensitivity measurement problem

Yes, this can be done.  You can also do a correlation between noise 
spectrum in a power supply rail and jitter spectrum in your transmit 
PLL.  The receive PLL is much harder, and depends on what you have 
access to.  Amherst offers software for this purpose.

Steve.
Huang chunxing wrote:
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> Hi experts,
>
> I am trying to find out whether it is possible to get the
> relationship between powernoise and output jitter by measurement.
> To be convenient, I would like to call it Power Noise sensivity.  
>
> My initial thought is to inject a certain frequency power noise
> on PLL power, and then measure SJ at the frequency on TX output signal. 
> But it is some difficult to be applied in practice due to PDN impedance 
> variance.
> Is there any craft method to avoid it?
>
> As to RX side, it is difficult to loop out clock recovered by CDR.
> I was ever been told that as TX and RX share same PLL, or use
> same design PLL, so power sensitivity at RX is similar with
> power sensitivity at TX. If we measure power sensitivity at TX,
> then we can get one at RX.
> Is that true, or could stand at most cases?
>
> I tried to find some documents for reference, but I failed.
> I hope experts here who ever did similar work may give me
> some comments and suggestions.
> Thanks in advance!  
>
>
> Regards,
>
> Huang Chunxing
> HUAWEI TECHNOLOGIES CO.,LTD.  
>
>
> Address: Huawei Industrial Base
> Bantian Longgang
> Shenzhen 518129, P.R.China
> Tel: +86 755 89651027 
> Fax: +86 755 89650600 
> E-mail: huangchunxing@xxxxxxxxxx
> www.huawei.com
>
>
>
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