[SI-LIST] Re: QUERRY
- From: John Barnes <jrbarnes@xxxxxxxxx>
- To: msunil@xxxxxxxxxxxxxxxx, si-list@xxxxxxxxxxxxx
- Date: Wed, 07 Apr 2004 11:03:12 -0400
Sunil,
I've used a 6-layer stackup like you show, on controller cards with
processor speeds up to 1.43GHz and 64-bit bus speeds up to 133MHz:
* Layer 1 = Topside components, vertical high-speed signals.
* 0.007 inch dielectric
* Layer 2 = Solid ground/return plane.
* 0.013 inch dielectric
* Layer 3 = Horizontal high-speed signals.
* 0.013 inch dielectric
* Layer 4 = Vertical low-speed signals.
* 0.013 inch dielectric
* Layer 5 = Partitioned power plane.
* 0.007 inch dielectric
* Layer 6 = Bottomside components, horizontal low-speed signals.
With 0.005 or 0.006 inch-wide traces we had about 60-ohm impedance in
all four signal layers to minimize impedance discontinuities when
switching from layers 1 to 3 (and vice versa) or 4 to 6 (and vice
versa). If we had a high-speed signal that went to layer 6, we kept the
traces on layer 6 very short, just long enough to via to the proper
layers. When we had to lengthen clock signals or other signals to match
their lengths, we used layer 3 wherever possible to take advantage of
its being stripline, with shielding planes above and below it. When
routing signals on layers 4 and 6, we tried to avoid crossing moats in
layer 5. As a general precaution, we stitched different power polygons
together with 100nF ceramic capacitors spaced about every 1 inch along
the moats. And when we had a slot in the ground/return plane or the
power plane because of anti-vias that were too close together, we ran
ground/power traces between pads to try to keep individual slots shorter
than about 0.3 inches. But be very careful when stitching the sides of
slots together, because on the first pass of my X820e card we
accidentally created a +3.3V-to-ground short in the artwork.
I cover many more PCB layout considerations in Robust Electronic
Design Reference Book, Volumes 1 and 2 , specifically:
* Chapter 31, Designing Printed Circuit Boards (102 pages, 58 figures,
3 tables).
* Appendix G, Important Properties of Printed Circuit Boards, Hybrid
Modules, Flat Cables, and Busbars (52 pages, 38 figures, 10 tables).
These books just came out two weeks ago today in the US, so I'm not sure
of their availability in India just yet. To the best of my knowledge
you will need to order them by mail, phone, or fax from:
Kluwer Academic Publishers Group
Post Office Box 322
3300 AH Dordrecht, THE NETHERLANDS
phone (31 78 6576 000)
fax (31 78 6576 254)
E-mail services@xxxxxxx
I have a web page about "Robust", including all the book sellers that I
am currently aware are carrying or will special order the books, at
http://www.r-e-d-inc.com/book-out.htm
I have another web page for corrections (2 so far), updates (0 so far),
and additions (1 so far) at
http://www.r-e-d-inc.com/errata.htm
John Barnes KS4GL, PE, NCE, ESDC Eng, SM IEEE
dBi Corporation
http://www.dbicorporation.com/
------------------------------------------------------------------
To unsubscribe from si-list:
si-list-request@xxxxxxxxxxxxx with 'unsubscribe' in the Subject field
or to administer your membership from a web page, go to:
//www.freelists.org/webpage/si-list
For help:
si-list-request@xxxxxxxxxxxxx with 'help' in the Subject field
List FAQ wiki page is located at:
http://si-list.org/wiki/wiki.pl
List technical documents are available at:
http://www.si-list.org
List archives are viewable at:
//www.freelists.org/archives/si-list
or at our remote archives:
http://groups.yahoo.com/group/si-list/messages
Old (prior to June 6, 2001) list archives are viewable at:
http://www.qsl.net/wb6tpu
Other related posts:
