[SI-LIST] Re: QDRII clock design
- From: Robert Kezer <Robert.Kezer@xxxxxxxxxxxxx>
- To: "'Jean_Pierre.Bouthemy@xxxxxxxxxx'" <Jean_Pierre.Bouthemy@xxxxxxxxxx>,si-list@xxxxxxxxxxxxx
- Date: Thu, 13 Nov 2003 08:36:15 -0500
Yes,
The input stage for a HSTL/SSTL clock input buffer is a differential animal.
Instead
of applying the vref signal, you apply the inverted clock signal.
Bob
-----Original Message-----
From: Jean_Pierre.Bouthemy@xxxxxxxxxx
[mailto:Jean_Pierre.Bouthemy@xxxxxxxxxx]
Sent: Thursday, November 13, 2003 5:38 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] QDRII clock design
Hi SI Experts,
Just a question:
Do you think that the following clock signals K/KN, C/CN (from FPGA to
QDRII) and CQ/CQN (from QDRII to FPGA) should be considered as differential
signals, with equal length in order to minimize skew, and thus routed as
differential signals with coupling (risk of crosstalk?).
Any comment will be welcome.
Thank you for your help.
Jean-Pierre.
--------------------------------------------------------------------------
Jean-Pierre BOUTHEMY
Hardware Design Engineer
ALCATEL - Mobile Networking Division (MCG)
Mobile Core R&D
+33 (0)2 99 26 08 18
mailto:jean_pierre.bouthemy@xxxxxxxxxx
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