[SI-LIST] Proposed Launch (was TDR Recommendations)

  • From: "Ray Haynes" <ray.haynes@xxxxxxxxxxxxxxxx>
  • To: "SI List" <si-list@xxxxxxxxxxxxx>
  • Date: Wed, 12 Nov 2003 17:31:02 -0700

Thanks for all the responses and I'm hope I'm not too green for this =
list.=20

Like I said in the previous post I'm new to this GHz stuff but I'm very =
resourceful. I wanted to answer a couple of questions and further =
clarify.=20

First I was asked if I had simulated the artwork. The answer is no. We =
don't have that capability currently. But knowing I'm not simulating, I =
design the artwork VERY conservatively. The I/O connectors are surface =
mount serial ATA connectors. There are no vias, just a fairly straight =
(~5") shot to the Virtex II Pro chip. The corners are well rounded and =
the spacing between traces and the ground plane were set by the fab =
house at 100ohm differential impedance. Crosstalk should not be a =
problem as all other signals have been kept far away.

For the TDR I was planning on building a launch PCB with coax connectors =
matching the TDR module to a serial ATA connector. I was going take a =
blank PCB and stuff only the serial ATA connector and connect it to the =
launch PCB with a serial ATA cable. Is there a flaw in my thinking?=20

I will study up on the TDT. =20

My overall thinking on this first try at a mulit-gigabit design is to go =
very conservative. Use hardware that is specified for higher than these =
frequencies, keep everything shorter then designed for. With limited =
funds for test gear I have to do some finger crossing. I'm trying reach =
a balance between the finger crossing and buying all the test gear I =
really want.


Ray Haynes
Phoenix, AZ


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