[SI-LIST] Re: Propagation delay question

Hi Dan,

I may be able to offer a little insight.  Generally AC timjing is done
using flight time measurements, where flight time contains both
propagation delay and delta tCO, where delta tCO is the change in tCO
under actual load vs the tCO test load. You obtain flight time by
subtracting tCO buffer delay into the test load from total delay from
the launch point to the receiver. Whether or not you include pkg
parasitics in your buffer delay simulation depends on how the baseline
tCO spec is defined for the driving device. SDRAMS define tCO to the pkg
pin and therefore you need to include package parasitics when you
simulate buffer delay into the test load. When you subtract this buffer
delay from total delay time you will then normalize flight time back to
the pin, where the baseline tCO is defined, thereby mainatining a
contiguous non-overlapping timing measurement path.  If however, your
driving device's baseline tCO is defined to the die-pad, as some memory
controllers are defined, then your buffer delay test circuit would not
include pkg parasitcis, and then when you subtract buffer delay from
total delay you normalize flight time back to the die-pad, and once
again maintain a contiguous non-overlapping timing path. Its not unusual
to include pkg parasitics in reads from the SDRAM, but not include them
in writes from the controller, becaseu of differences in how baseline
tCO is defined. =20


Brian P. Moran =20
Intel Corporation=20
brian.p.moran@xxxxxxxxx=20


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx [mailto:si-list-bounce@xxxxxxxxxxxxx]
On Behalf Of Dan Bostan
Sent: Monday, January 31, 2005 11:48 AM
To: Stephen Zinck; 'Si-List'
Subject: [SI-LIST] Re: Propagation delay question

Stephen,
I am using a typical DDR PTP topology, with a series termination and a
parallel termination to VTT, with two IOs, one for an ASIC and one for
the memory.
Since I am simulating AND measuring at the pin, I do not see how the
package parasitics play here.
And, yes, I am measuring at exaclty the same threshold voltage.
The slew rate is different, since I have two different IOs.
Thanks,
/dan

--- Stephen Zinck <signalintegrity@xxxxxxxxxxx> wrote:

> Hi Dan,
>=20
> Maybe you could give the list a little more detail as far as the=20
> topology, etc for the circuit in question.
>=20
> But off the cuff, my guess would be loading differences between=20
> bi-directional drivers. You may have two loads at the memory and one=20
> at the controller. Package models may be sufficiently different to=20
> cause some the delay differences you are seeing as well. Finally, you=20
> may have a single parallel term down one end (near the SDRAM) or two=20
> series terms with different values that could cause edge-rate=20
> differences, which would manifest itself as different delay=20
> characteristics depending on drive direction. By the way, how are you=20
> measuring delay (i.e. to the vdd/2 threshold point, etc.?)?
>=20
> Regards,
> Steve
>=20
> Stephen P. Zinck
> Interconnect Engineering
> 25 Bennett Lot Road
> South Berwick, ME 03908
> Phone - (207) 384-8280
> Fax - (207) 384-5388
> Email - szinck@xxxxxxxxxxxxxxxxxxxxxxxxxxx
> Web - www.interconnectengineering.com
>=20
>=20
> ----- Original Message -----
> From: "Dan Bostan" <dbostan@xxxxxxxxx>
> To: "'Si-List'" <si-list@xxxxxxxxxxxxx>
> Sent: Monday, January 31, 2005 2:20 PM
> Subject: [SI-LIST] Propagation delay question
>=20
>=20
> > Fellow SI members,
> > Could anyone explain to me why the propagation
> delay,
> > simulated and measured at the pin, on a
> bidirectional
> > DQS line, for a DDR memory, is different for a
> write
> > cycle vs. a read cycle?
> > Obviously, the transmission line is identical,
> only
> > the drivers are different.
> > /dan
> >
> >
> >
> >
> >
> > __________________________________
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>=20
>=20



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