[SI-LIST] Re: Propagation delay question

 =0D =0D 
Dan -=0D 

Many DIMMs have programmable drive strength. Are the controller and= memory
using the same class of buffer? The memory should default to SSTL_2= class
II.

Bob

On Mon Jan 31 13:20 , Dan Bostan sent:

=0D Fellow SI members, Could anyone explain to me why the propagation delay,
simulated and measured at the pin, on a bidirectional
DQS line, for a DDR memory, is different for a write
cycle vs. a read cycle?
Obviously, the transmission line is identical, only
the drivers are different.
/dan





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