[SI-LIST] Propagation delay question
- From: Dan Bostan <dbostan@xxxxxxxxx>
- To: 'Si-List' <si-list@xxxxxxxxxxxxx>
- Date: Mon, 31 Jan 2005 11:20:29 -0800 (PST)
Fellow SI members,
Could anyone explain to me why the propagation delay,
simulated and measured at the pin, on a bidirectional
DQS line, for a DDR memory, is different for a write
cycle vs. a read cycle?
Obviously, the transmission line is identical, only
the drivers are different.
/dan
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- Follow-Ups:
- [SI-LIST] Re: Propagation delay question
- From: Stephen Zinck
- References:
- [SI-LIST] Plane breaks - Benchmark report download
- From: Sam Chitwood
Other related posts:
- [SI-LIST] Re: Propagation delay question
- From: Stephen Zinck
- [SI-LIST] Plane breaks - Benchmark report download
- From: Sam Chitwood