[SI-LIST] Problems with system bus design

Hello,
I am using a 32-bitprocessor in current design. 
 I have one technical doubt about system bus design.
In processor data sheet, in DC Electrical
Specification section, it is mentioned that drive
capability of data bus is 6 mA and output load is of
30 pF. I am referring a book "High Speed Digital
Design; A hand book of Black Magic" by Howard Johnson
for peripheral bus analysis. As per formulas given in
this book i found that it is not possible for
processor peripheral data bus to drive 30 pF load with
6 mA drive capability and meet rise time requirement
of 1.5 nS. The design calculations are as follows,

Output driver resistance = (VCC- VOH)/IOH =
(3.3 - 2.4)/ 6 mA = 150 ohm
So rise time = 2.2*R*C = 2.2*150*30pF 
= 9.9 nS    

I have a lot of confusion about these calculations.

Hoping for a quick reply

Thanks and Regards
pomgud
    

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