[SI-LIST] Problems with high speed link

Hi,
I have some thoughts about the limits to high speed links. Since I currently 
don't have industrial experience in this field, could someone comments on them 
with his/her industrial insights? Thanks!

From the SI books and papers, I understand that dielectric loss dominates the 
transmission line loss over skin effect loss at high frequencies. If we define 
FC as the frequency where the two loss mechanisms equal, then for conventional 
FR4 board, FC should be around 1G, which means for high speed link >10Gb/s, 
dielectric loss is dominant on FR4 boards. But if more expensive materials such 
as Rogers are used, this FC will be tens of GHz. Does this mean that for 
<50Gb/s links, if high performance materials are used, the optimization should 
be to minimize the skin effect loss? And once the loss tangent is below for 
example 0.002, it doesn't help much to reduce it even further. Is that true?

Or for links <50G, neither skin effect loss nor dielectric loss is dominant. 
Instead, the vias, connectors and packages will be the major bottlenecks. So 
the emphasis should rather be put on 3D optimization of those transitions.


      

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