[SI-LIST] Re: Power plane frequency range and noise level

  • From: =?big5?b?SG91S2V2aW4oq0ql/qaoKQ==?= <HouKevin@xxxxxxxxxx>
  • To: "'John@xxxxxxxxxxxx'" <John@xxxxxxxxxxxx>, si-list@xxxxxxxxxxxxx,"Larry.Smith (E-mail)" <Larry.Smith@xxxxxxx>
  • Date: Wed, 22 Oct 2003 20:02:51 +0800

Hi john:
I haven't seen you for a long time!
How are you reently!


Let me try to answer your question.

about power integrity on the board,  the low frequency range is covered by
VRM design (depend on Rout,Lout,Rflat,Lslew)
and the  high frequency range is covered by IC's(like as CPU)  package.
We can do nothing above 50 MHz from PCB level.the package and chip level
should handle that power noise.
All we have to do is to choose how many bulk caps ,ceremic caps and what
value.
of course,good power/GND pair design(physical shape) is helpful to lower
power noise at very high frequency range.
Because you can condider the PWR/GND pair as a big capacitor.

The bulk cap is useful to lower dynamic impedance at 1K~1M range.the ceremic
is applied to 1M~50M.
But ,as you know,the lower cap's value ,the higher  ESR value,so decap is
more and more no effective on power integrity.

As for the guideline to power noise you mentioned,it depends on how much IC
can stand.For CPU's example
usually,you can check CPU's datasheet(the relative EMTS of intel),the DC
characteristic point out the tolerance.
or find out that from the relative VRM design request of intel published.
My remebrance is 5%.

if i have some mistake,feel free to let me know.thank you!

KEVIN hou 
assistant manager
High Speed Signal Design Division 
RD7 , PSBU 
MiTAC Computer Inc. 
* 886-3-396-2888 Ext. 3231 
* 886-3-327-7262 
* houkevin@xxxxxxxxxx <mailto:houkevin@xxxxxxxxxx>  

 



-----Original Message-----
From: John Lin (ªL´Â·×) [mailto:John@xxxxxxxxxxxx]
Sent: Wednesday, October 22, 2003 5:52 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Power plane frequency range and noise level


Dear all SI gurus,
Could some one comment on what range of frequency we need to care for a
power plane simulation? 
For example, for a power plane to support a chip with 800Mhz bus transition.
What is the frequency range I need to set for simulation?

And if the bus is 1.5voltage type, is ther any guideline to say the amount
noise allowed on the power plane?

Thank you for helps in advance.

Best Regards
John.


 


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