[SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator)

Bart,

I think you are absolutely correct about the differences between
differential pair signaling and single-ended signaling with regard to return
current flow in the PCB ground plane (or cable shield for that matter).

Colleagues of mine presented a paper at last year's IEEE EMC Symposium that
demonstrated this.  The experiment was a transmission line on a multilayer
PCB where the return current had to "jump layers" to get back to its source.
The difference in effect on differential signals and signle-ended signals is
dramatic. For interested persons, the paper's particulars are:

Fan, Jun, James L. Knighten, Norman W. Smith, Ray Alexander, and Deborah
Dressler, "The Effects of Signal Layer Positions in Multi-Layer PCB
Designs," 2002 IEEE International Symposium on Electromagnetic
Compatibility, Minneapolis, MN, August 19-23, 2002, pp. 320-324.

While differential transmission lines do cause circulating currents on
return planes, there is no net longitudinal return current unless you have
imbalance.  For single-ended transmission lines, the net longitudianl return
current equals the outgoijng current on the strip.

Jim

________________________
James L. Knighten, Ph.D.
Teradata, a division of NCR                 http://www.ncr.com
17095 Via del Campo
San Diego, CA 92127
tel: 858-485-2537
fax: 858-485-3788


-----Original Message-----
From: McCoy, Bart O. [mailto:McCoy.Bart@xxxxxxxx] 
Sent: Wednesday, August 20, 2003 7:34 AM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass
Capacitor Caculator)


Well, I'm no expert here, but Larry does bring up a good point 
in bringing up return-current induced power-plane bounce.   
Something that  may be helpful to consider with respect to return-current 
induced power plane bounce is the use of differential signaling.

From many electromagnetic simulations and experiments (and 
lab data that supports it) I have seen considerable return-current 
advantages (from the standpoint of SI) when using differential pairs 
simply because differential return currents recirculate at interface 
boundaries.  

For example, if you have several sets of differential pairs 
cascaded together (each with a reasonable ground) separated by
any type of boundary (silicon to board;  board to board; flex to board;
small breaks in the ground plane; etc. ) differential return currents 
need not and will not usually cross these boundaries because of the 
strong tendency for them to recirculate and meet up with and cancel it's 
neighboring return current of equal magnitude and in opposite phase
(direction).   In fact, if you DO make ground connections
via wirebonds, connectors, etc. to cross an interface boundary, 
the little electrons comprising ground return currents sliding under each 
leg of the differential pair will usually ignore you and glide down the 
path of least impedance- which is cancelling with the equal and opposite 
return current of the leg in the diff pair-- not crossing the lossy
interface boundry through wirebonds, etc.

I've seen many cases in the lab verifying this.  In one specific case 
I had a differential pair crossing from a flex to a PCB, for example, 
where the ground connections were completely unnecessary.  This allowed
100% ground isolation between flex/board (in my particular case) because the

signal was the only thing I needed to share between boards- not grounds.
At a minimum, if you have multiple ground systems, it leaves you with the
option 
of getting ground from a better source and not have ground paths leak over 
through your signal interconnects.

Switch to single-ended systems and you are forced to content with shared 
ground systems because the return current must recirculate through the 
entire length of your signal and must cross all media boundaries.  
Then you're forced to contend with all the power-supply bounce/decoupling
issues 
associated with that.

Just a thought that may be helpful in some particular cases- it's not a 
fix-all for return-current induced power-supply bounce.


  - Bart McCoy




-----Original Message-----
From: Larry Smith [mailto:larry.smith@xxxxxxx] 
Sent: Tuesday, August 19, 2003 12:57 PM
To: Zhihui Wang
Cc: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Re: Power Integrity (was: UltraCAD ESR and Bypass
Capacitor Caculator)


Zhihui - You are correct, if there are design problems in the package
that create SSO/SSN, there is very little that can be done about it at
the PCB level.  The most important thing that the package designer can 
do is insure that there is continuous return current for all signal 
traces, otherwise, we don't have a controlled impedance within the package.
The package trace may appear to be 50 ohms from the trace geometry
over a reference plane, but if the return current path is not continuous,
the trace impedance is not controlled.  

The problem is even more difficult at the PCB to package interface.  The
PCB designer often does not know which package return plane will carry
signal return current (Vdd or Gnd).  The package designer hardly ever knows
which PCB plane will carry return current.  We may have perfectly designed
50 ohm traces on both the package and PCB but fail to have a controlled
impedance environment because return current is discontinuous as signal
current jumps between the PCB and package.  Note that this is an SI problem
rather than a PI problem.  The power integrity may be perfect, meaning that
local Vdd-Gnd is a constant value at the PCB, package and chip levels.  But
the reference planes may jump wildly with respect to each other across the
physical boundaries if the return current path is not carefully designed.
This is the modern SSN problem.  For a few dozen signals, this is generally
not a problem.  But some of our ASIC and processor packages have more than
1000 I/O.  Serious power plane bounce can occur if a majority of these
signals decide to switch the same way at the same time.

Decoupling capacitance at the PCB and package level can help this, but
parasitic inductance really gets in the way.  The signal edges are hurt
the worst by the lack of continuous return current.  The frequency content
is typically in the GHz range, but inexpensive discrete decoupling
capacitors
become ineffective above 100 MHz.  This is where thin power plane
dielectrics
can really help us at the PCB and package levels.  Displacement current
between the planes can carry the signal return current but at the expense
of power plane bounce.  The bounce is proportional to the distance between
Vdd and Gnd power planes.  Embedded package capacitance can help also, but
parasitic inductance must be considered.

This is the classic place where power integrity gets mixed up with signal
integrity.  There may be more than sufficient decoupling capacitance at
the chip, package and PCB levels to make the power supply rock solid for
current transients drawn by the silicon (PI).
But power plane bounce due to signal return currents can create 
SI and EMI problems that are difficult to control with discrete capacitors.

As Chris Cheng suggested earlier, a continuous ground path can help this
situation.  But for system costs or other reasons, very few of us are
willing to have ALL of our return current on ground.  If return current
ever gets onto a Vdd reference plane, it will inevitably have to jump planes
somewhere along the signal path.  Certainly at the driver, return current
for a rising edge is on Vdd and for a falling edge is on ground.  Return
currents at edge frequencies are going to have to go through a decoupling
capacitance somewhere.  The same arguments can be made at terminating
resistors
located at the receiving end.

regards,
Larry Smith
Sun Microsystems

Zhihui Wang wrote:
> 
> Hi Larry,
> 
> You gave a highly brief summary about Power Integrity in different level.
Great!
> If the package power delivery system was not good designed, it is hard to
reduced
> SSO in PCB side, sometimes it is impossible. Package SSO/EMI issue often
happened
> on
> high pin count package, which means high IO numbers, such as
microprocessor,
> ASIC and FPGA, etc. Most of the package related to these ICs are laminate.
> I am thinking can we design a "smart" package structure which is kind of
> on-package
> decoupling capacitor likely, just like we often design embedded passive
inductor
> in the package.
> And this kind of structures are used to replace on-package decap.
> You have done a lot of research work on pwr/gnd plane modeling, do you
think it is
> possible or not?
> Does any experts in this list has ideas or experience in this idea?
> 
> Thanks
> Zhihui Wang
> AMI Semiconductor
> 
> Larry Smith wrote:
> 
> > Vishram - I agree.  My general approach is to address the PI problem
first
> > and make sure that the silicon circuits have clean power.  This involves
> > management of capacitance and inductance at the PCB, package and chip
levels.
> > Next, address the SI problems by making sure that all high speed signals
have
> > a good return current path.  After doing these two things, many EMI
problems
> > will be eliminated.
> >
> > I have also been able to fix EMI problems at multiple 100's of MHz by
> > using decoupling capacitors.  But the higher the frequency gets, the
> > harder it is to do this.  Capacitors at this frequency usually will not
affect
> > the quality of the power as measured at the silicon circuit terminals
(PI),
> > but they might effect emmissions.
> >
> > After we began using thin power plane
> > dielectrics, I don't believe we have found any EMI problems that can
> > be fixed with discrete decoupling capacitors.  But if your product does
> > not have thin power plane dielectrics (4 mil or less) for cost or
> > other reasons, EMI problems can _sometimes_ be fixed with caps.  If
> > this works, it is usually not a very robust solution.  If some little
> > thing changes, the EMI problem often crops back up again.
> >
> > regards,
> > Larry Smith
> > Sun Microsystems
> >
> > Vishram Pandit wrote:
> > >
> > >
> > > Larry,
> > >
> > > Very nice explanation. PI influences SSN, and SSN influences EMI. EMI
is
> > > influenced by PI and SI. If we have sound PI and also, reduce the SSN,
then
> > > EMI (due to that aspect of the circuit) is mitigated. Would you agree?
> > >
> > > As mentioned in my pevious mails, I have seen improvements in EMI at
higher
> > > frequencies (as high as 800MHz) with decoupling capacitors, and
changing the
> > > P/G structure to improve the impedance. Your email states that PI is
> > > characterized by P/G impedance and decaps for PI are effective up to
100MHz.
> > > However, in my case, I reduced the 800MHz impedance further by decaps
> > > betweenP/G, and by improving the P/G strucutre, and it helped improve
the
> > > EMI. Thus, improving PI at 800MHz improved the EMI.Apart from chaning
the
> > > structure of P/G, decaps (value, ESL, locations) played important part
in
> > > it.
> > >
> > > I will appreciate your comments.
> > >
> > > Thanks,
> > >
> > > Vishram Pandit
> > >
> > > Senior Member Techincal Staff
> > >
> > > Hughes Network Systems
> > >
> > >   >From: Larry Smith >Reply-To: Larry.Smith@xxxxxxx >To:
> > > si-list@xxxxxxxxxxxxx, Charles.Grasso@xxxxxxxxxxxx >Subject: [SI-LIST]
Power
> > > Integrity (was: UltraCAD ESR and Bypass Capacitor Caculator) >Date:
Fri, 15
> > > Aug 2003 14:04:39 -0700 (PDT) >>I changed the thread name to better
reflect
> > > the subject.. >>Some of us at Sun have begun using a different word
for the
> > > power >distribution problem, "power integrity." This phrase helps to
> > > >distinguish three major topics: power integrity (PI), signal
integrity
> > > >(SI)and EMI. Power integrity is the issue that Charles is addressing
>and
> > > signal integrity is what Kim is addressing in his very nice web
>posting. A
> > > lot of the confusion could be eliminated by using clearer
>terminology. >>I
> > > think of the "power integrity" problem as having only two nodes: Vdd
>and
> > > Gnd. There are no signals involved. For the power integrity >problem,
we are
> > > concerned with delivering many watts of power, often at >low voltage
and
> > > highcurrent, to modern digital technology. The big >issues are
transient
> > > current and DC loss. A good example is an >advanced micro processor
that
> > > draws as much as 100 watts of power at 1 >volt (100 amps). The
processor can
> > > go from an idle state to a fully >active state in just a few clock
cycles (1
> > > nSec). The silicon circuits >may consume 50 amps and then 100 amps
just a
> > > fewcycles later. >Delivery of this 50 watt transient through the
various
> > > timeconstants, >which range from nSec to mSec (chip, package, PCB,
VRM, AC
> > > toDC >converter), is very much a part of the power integrity problem.
Note
> > > >that 1 mOhm of DC resistance in this circuit consumes 10 watts of
power
> > > >(I^2*R) and renders our delivery system only 90% efficient. Power
> > > >Integrityinvolves delivering high current with huge transients. It is
>best
> > > understood and managed by the concept of target impedance in the
>frequency
> > > domain. >>Signal integrity, on the other hand, always involves signal
nodes.
> > > A >few years ago, at the 50 MHz level, signal integrity basically
meant >the
> > > waveform quality and timing on ideal transmission lines. Before >that,
all
> > > wehad to worry about (at the 5 MHz level) was RC time >constants. Now
we are
> > > beyond 500MHz where we must be concerned with >frequency dependent
loss and
> > > return current paths. Several years ago, >SSN (simultaneous switch
noise)
> > > wasmostly an L*di/dt problem that >created ground bounce in the DIP's
(dual
> > > inline packages, lead >frames). After we started including ground
planes in
> > > our packages, >replaced wire bonds with solder bumps and started using
just
> > > as many >ground pins as signal pins, the SSN problem changed to a
power
> > > plane>bounce and return current problem. This is how power integrity
keeps
> > > >getting mixed up with signal integrity. The return current for
signals >is
> > > on power and/or ground planes. But we can avoid a lot of confusion >if
we
> > > usethe term "power integrity" for topics that involve just Vdd >and
ground
> > > and reserve "signal integrity" for topics that involve >signal nodes.
> > > >>Decoupling capacitors play a role in all three topics. For the power
> > > >integrity problem, they are energy storage devices that mitigate
power
> > > >transients. They deliver energy when the voltage droops and store
>energy
> > > when the voltage spikes. For the signal integrity problem, they
>enable
> > > return current to jump from one node to another (i.e. Vdd1 to >Vdd2 or
Vdd
> > > toGnd) when packages, vias or connectors require signal >return
current to
> > > make the jump. For the EMI problem, they provide low >impedance and
energy
> > > absorption at frequencies where the product >naturally has a lot of
energy
> > > (clock) or frequencies where the product >has a very efficient
resonator or
> > > radiator. >>Decoupling capacitors are effective for the power
integrity
> > > problem in >the 100 kHz to 100 MHz frequency band. Below 100 kHz it
takes
> > > toomany >uF for them to be effective and above 100 MHz their
inductance gets
> > > in >the way. However, decoupling capacitors may be used to complete
return
> > > >current paths (SI) or absorb noise (EMC/EMI) up to much higher
> > > >frequencies.Below 50 MHz, position on the PCB is not very important
>but
> > > above 200 MHz, position often becomes critical. Thin power plane
> > > >dielectricsare a good replacement for discrete decoupling >capacitors
that
> > > are aimed at frequencies above 100 MHz. Power plane >capacitance is
"broad
> > > band" but the Q of discrete capacitors becomes >sharp and limits their
> > > effectiveness as frequency increases. >>Very few topics on SI-list
seem to
> > > evoke as many emotions as decoupling >capacitors. That is probably
because
> > > people view them from so many >different perspectives. Vastly
different
> > > conclusions can be drawn for >decoupling capacitors depending on the
problem
> > > you are trying to solve >(PI, SI or EMI) and other variables such as
power
> > > plane dielectric >thickness. Some of this can be helped by clearly
defining
> > > the >terminology and use conditions. >>regards, >Larry Smith >Sun
> > > Microsystems >>>Delivered-To: si-list@xxxxxxxxxxxxx >>From: "Grasso,
> > > Charles">>To: "'si@xxxxxxxxxxxx'" , "'si-list@xxxxxxxxxxxxx'"
>>>Subject:
> > > [SI-LIST] Re: UltraCAD ESR and Bypass Capacitor Caculator >>Date: Thu,
14
> > > Aug2003 15:39:34 -0600 >>MIME-Version: 1.0
>>Content-Transfer-Encoding: 8bit
> > > >>X-archive-position: 7937 >>X-ecartis-version: Ecartis v1.0.0
> > > >>X-original-sender: Charles.Grasso@xxxxxxxxxxxx >>X-list: si-list
>>>>Hi
> > > Kim, >>First - thanks for putting the slides up on the bweb for >>all
to
> > > see.I think that you may have missed the point >>a little. In your
scenario
> > > (a signal trace switching >>planes )the location of the caps is vital.
> > > >>>>The discussion was centered on the location of caps >>wrt power
> > > distribution. The location of the capacitors >>(within reason) will
not
> > > affect a S11/S21 measurement >>that much. >>>>Fancy tackling that
little
> > > problem? >>>>Best Regards >>Charles Grasso >>Senior Compliance
Engineer
> > > >>Echostar Communications Corp. >>Tel: 303-706-5467 >>Fax:
303-799-6222
> > > >>Cell: 303-204-2974 >>Email: charles.grasso@xxxxxxxxxxxx; >>Email
> > > Alternate:chasgrasso@xxxxxxxx
> > > >>------------------------------------------------------------------
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