[SI-LIST] Re: Potentially Dumb Question About Routing Layers

Tim,
Happens all the time, especially as modern ASICs or FPGAs may require several 
different I/O rails. You can't spend a plane pair on all of them, nor suffer 
split-crossings if you cut up and share a reference layer. A shape on a routing 
layer can make perfect sense. Something to ask yourself though, is how much 
extra pFs / reduction in PDN impedance am I really getting from this tiny shape 
as opposed to say a fat trace?

-peter arnold


-----Original Message-----
From: si-list-bounce@xxxxxxxxxxxxx on behalf of Nash, Timothy J
Sent: Wed 11/03/2009 4:49 PM
To: si-list@xxxxxxxxxxxxx
Subject: [SI-LIST] Potentially Dumb Question About Routing Layers
 
SI Gurus:
 

How common is the practice of sharing a routing layer with a power or
ground region (i.e. an FPGA core voltage plane)?  If I can find a
reasonable return path for the signals, at face value, it appears to be
ok.  But something screams inside of me that this isn't a good idea, but
I can't really explain why.

 

Thanks in advance,

Tim



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