[SI-LIST] Re: Post Layout Signal Integrity Analysis

Hi Gafni!
 I visited the Cadence WEB 
(http://www.cadencepcb.com/products/specctraquest/whatsnew.asp) and found  the  
following information:

Create/use SPECCTRAQuest high-speed design kits containing (encrypted) HSPICE 
models
SPECCTRAQuest now provides the ability to create high-speed design kits 
containing encrypted HSPICE models. Direct use of silicon-level HSPICE models 
within SPECCTRAQuest enables the concurrent design of ICs and PCBs and allows 
design kits to be created 20 times faster than before. This also provides a 
solution for engineers to perform PCB simulation with a new breed of complex 
models that cannot be represented in IBIS-style formats. This capability is 
available only to design kit creators and design kit consumers. Contact your IC 
Company that provides you with (encrypted) HSPICE models to get a SPECCTRAQuest 
design kit that encapsulates HSPICE models. 

good lucky

Johnson Hu


----- Original Message ----- 
From: "Scuba Snail" <scubasnail@xxxxxxxxxxx>
To: "SI_LIST (E-mail)" <si-list@xxxxxxxxxxxxx>
Sent: Thursday, June 27, 2002 1:53 AM
Subject: [SI-LIST] Post Layout Signal Integrity Analysis


> Hello Experts,
> 
>  
> 
> As part of our design process, we conducted a pre-layout analysis and 
> simulations.
> 
> Using the results, we have concluded about the traces length, width, topology 
> and so.
> 
> We used this data to constrain the layout (we are using ALLEGRO).
> 
> For the most part, we used HSPICE for the SI simulations.
> 
>  
> 
> Now we are at the point that the layout is about to be ended, and we seek a 
> method to perform a post-layout simulations.
> 
> 1. Does anyone now of a way to combine the HSPICE and the ALLEGRO?
> 
> 2. Does anyone have any recommendations at all for what to do or not to do?
> 
>  
> 
> I appreciate your time and knowledge.
> 
> 
> 
> Thanks 
> 
> 
> 
> Gil Gafni
> 
> 
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